Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery

Triple Modular Redundancy (TMR) applied with various granularity combined with periodical scrubbing of a configuration memory or with run-time Partial Dynamic Reconfiguration (PDR) for fault recovery are one of the most preferred Single Event Upset (SEU) mitigation techniques used by Fault Tolerant Systems (FTS) implemented into SRAM-based FPGAs. Usage of PDR and TMR allows recovering of FTSs from all transient SEU faults and offers run-time fault mitigation compared to scrubbing methods which only correct configuration upsets and are limited by scrubbing period latency. Reconfigurable TMR architecture may require global state maintenance after PDR is applied for fault removal. In such situation, operational state of reconfigured circuit copy needs to be synchronized with remaining circuit copies which were active during PDR. This paper evaluates existing synchronization methods for reconfigurable TMR architectures and soft-core processors; presents our recent research focused on a state synchronization methodology compared to the state of the art methods and further investigates strategy for a state synchronization of TMR-protected soft-core processor neo430.