Detail výsledku
Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks
Lojda Jakub, Ing., Ph.D., UPSY (FIT)
Pánek Richard, Ing., Ph.D., UPSY (FIT)
Čekan Ondřej, Ing., Ph.D., UPSY (FIT)
Krčma Martin, Ing., Ph.D., UPSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., UPSY (FIT), UTKO (FEKT)
This research paper presents examination of the influences of faults on a control unit of smart electronic locks. A stepper motor is often used as an actuator of such smart locks and its motor controller is usually implemented in a processor. The aim of this paper is to examine the impact of faults occurring in the control processor. It should be noted that faults in such electronic systems can also be induced artificially, usually with ulterior motives. The processor can be implemented in an FPGA (Field Programmable Gate Array) in order to be able to emulate HW faults inside the processor. This allows us to use previously developed evaluation platform for fault tolerance testing. This platform allows us to monitor impact of faults both on electronic and mechanical parts of electro-mechanical system. In this paper, the evaluation of faults artificially injected in FPGA-based processor is proposed. Experiments with both single and multiple fault injections were held.
Electronic Lock, Stepper Motor, FPGA, Fault Tolerance,
Fault Injection
@inproceedings{BUT162658,
author="Jakub {Podivínský} and Jakub {Lojda} and Richard {Pánek} and Ondřej {Čekan} and Martin {Krčma} and Zdeněk {Kotásek}",
title="Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks",
booktitle="2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)",
year="2020",
pages="1--4",
publisher="IEEE Circuits and Systems Society",
address="San José",
doi="10.1109/LASCAS45839.2020.9068977",
isbn="978-1-7281-3427-7",
url="https://www.fit.vut.cz/research/publication/12080/"
}