Detail výsledku

Design and Implementation of the Memory Scheduler for the FPGA - Based Router

MAREK, T.; BRYAN, L.; NOVOTNÝ, M. Design and Implementation of the Memory Scheduler for the FPGA - Based Router. Proc. of the Field Programmable Logic and Application 2004. Leuven: Springer Verlag, 2004. p. 1133-1139. ISBN: 3-540-22989-2.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Marek Tomáš
Bryan Luděk, Ing., Ph.D., FIT (FIT), UPSY (FIT)
Novotný Martin
Abstrakt

This paper deals with a design of a memory scheduler as a part of the Liberouter project.

Klíčová slova

FPGA, DDR SDRAM, memory, router, IPV6

Rok
2004
Strany
1133–1139
Sborník
Proc. of the Field Programmable Logic and Application 2004
Konference
The International Conference on Field- Programmable Logic and Applications
ISBN
3-540-22989-2
Vydavatel
Springer Verlag
Místo
Leuven
BibTeX 
@inproceedings{BUT17581,
  author="Tomáš {Marek} and Luděk {Bryan} and Martin {Novotný}",
  title="Design and Implementation of the Memory Scheduler for the FPGA - Based Router",
  booktitle="Proc. of the Field Programmable Logic and Application 2004",
  year="2004",
  pages="1133--1139",
  publisher="Springer Verlag",
  address="Leuven",
  isbn="3-540-22989-2"
}
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru