Detail výsledku

Web-Based Simulator of Superscalar RISC-V Processors

Vznik: 2024
Typ
software
Jazyk
anglicky
Autoři
Majer Michal, Ing.
Horký Jakub, Ing.
Vávra Jan, Ing.
Jaroš Jiří, prof. Ing., Ph.D., UPSY (FIT)
Popis

Unlock the power of superscalar processor design with our cutting-edge RISC-V simulator! Tailored for IT students, researchers, and HPC professionals, this web-based tool brings complex architectures to life with an intuitive, customizable interface. Explore processor components, tweak configurations, and benchmark code snippets-all from your browser.

The simulator offers seamless support for C and assembly programs, built-in performance metrics, and full GCC compiler integration for various optimization levels. Whether you're learning or innovating, this tool enables you to experiment with different architectural setups, analyze results, and export configurations for sharing.

Designed to deepen your understanding of processor design and HW-SW co-design, the simulator supports both interactive exploration and batch processing via command-line. Perfect for those aiming to optimize RISC-V processors and HPC codes, it's more than just a learning tool-it's a powerful platform for research and development. Get ready to elevate your skills and performance optimization with this advanced simulator!

Klíčová slova

RISC-V, Superscalar processor, Web application, simulation, architecture, performance metrics.

Umístění
Licence
K využití výsledku jiným subjektem je vždy nutné nabytí licence
Licenční poplatek
Poskytovatel licence na výsledek nepožaduje licenční poplatek
Licenční podmínky

Software je distribuován pod GNU GPL Licencí verze 3.0: https://www.gnu.org/licenses/gpl-3.0.html

Projekty
Application-specific HW/SW architectures and their applications, VUT, Vnitřní projekty VUT, FIT-S-23-8141, zahájení: 2023-03-01, ukončení: 2026-02-28, řešení
Výzkumné skupiny
Pracoviště
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