Detail výsledku

Fault Tolerant CAN Bus Control System Implemented into FPGA

SZURMAN, K.; KAŠTIL, J.; STRAKA, M.; KOTÁSEK, Z. Fault Tolerant CAN Bus Control System Implemented into FPGA. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013. Karlovy Vary: IEEE Computer Society, 2013. p. 289-292. ISBN: 978-1-4673-6136-1.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Szurman Karel, Ing., Ph.D., UPSY (FIT)
Kaštil Jan, Ing., Ph.D., FIT (FIT), UPSY (FIT)
Straka Martin, Ing., Ph.D., FIT (FIT)
Kotásek Zdeněk, doc. Ing., CSc., UPSY (FIT), UTKO (FEKT)
Abstrakt

For various types of applications, it is necessary to guarantee maximal level of fault tolerance and high reliability of components, avionic and railway applications can serve as an example of these applications. In these devices, electronic components are exhibited to the environment conditions, from among them especially cosmic radiation can have an undesired and destructive effect. In this paper, the basic ideas of the design and implementation of CAN bus based control system into FPGA platform is described. The bus control system uses CANAerospace application protocol. The fault tolerance features of the developed system are improved by TMR architecture. Then, experiments with SEU injection into both non-TMR and TMR architectures are described, the results presented and evaluated. In these experiments, SEU injection framework developed during our previous research was used which injects SEU failures into running FPGA design.

Klíčová slova

CAN, bus, CANAerospace, TMR, FPGA, SEU

Rok
2013
Strany
289–292
Sborník
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013
Konference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013
ISBN
978-1-4673-6136-1
Vydavatel
IEEE Computer Society
Místo
Karlovy Vary
DOI
10.1109/DDECS.2013.6549837
BibTeX 
@inproceedings{BUT192877,
  author="Karel {Szurman} and Jan {Kaštil} and Martin {Straka} and Zdeněk {Kotásek}",
  title="Fault Tolerant CAN Bus Control System Implemented into FPGA",
  booktitle="IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013",
  year="2013",
  pages="289--292",
  publisher="IEEE Computer Society",
  address="Karlovy Vary",
  doi="10.1109/DDECS.2013.6549837",
  isbn="978-1-4673-6136-1"
}
Projekty
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, zahájení: 2011-01-01, ukončení: 2015-12-31, ukončen
Metodiky pro návrh systémů odolných proti poruchám do rekonfigurovatelných architektur - vývoj, implementace a verifikace, MŠMT, COST CZ (2011-2017), LD12036, zahájení: 2012-03-01, ukončení: 2015-11-30, ukončen
Pokročilé bezpečné, spolehlivé a adaptivní IT, VUT, Vnitřní projekty VUT, FIT-S-11-1, zahájení: 2011-01-01, ukončení: 2013-12-31, ukončen
Výzkumné skupiny
Výzkumná skupina Spolehlivé číslicové systémy (VZ DEPSYS)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru