Reconfigurability of the Interconnect Architecture for Chip Multiprocessors

As multiprocessors on a single chip are penetrating quickly new application areas in network and media processing, their optimum interconnect architecture is of interest. A fixed application-specific interconnect may provide sufficient performance in some cases, but nowadays one can also consider the use of run-time reconfigurable interconnect to speed-up specific communication patterns during execution of the algorithm. The paper promotes the idea that the performance improvement can result mainly from changing interconnect topology for local and global communication patterns. Some examples of reconfigurable interconnect, clarifying this concept, are presented and a required area overhead is discussed.