Detail výsledku

On Distribution of Testability Values in Scan-Layout State-Space

STRNADEL, J. On Distribution of Testability Values in Scan-Layout State-Space. Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics. Košice: The University of Technology Košice, 2006. p. 308-313. ISBN: 80-8073-598-0.
Typ
článek ve sborníku konference
Jazyk
anglicky
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Abstrakt

In the paper, it is shown how are testability values distributed within the scan-layout state-space for particular digital circuit. The goal of the paper was to approve or dismiss our hypothesis that the more registers are included in greater number of multiple scan-chains within particular scan-layout,
the better testability properties correspond to the scan-layout.

Klíčová slova

digital circuit diagnostics, register-transfer level, circuit data-path, testability analysis, design for testability, testability improvements, scan technique

Rok
2006
Strany
308–313
Sborník
Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics
Konference
7TH International Scientific Conference Electronic Computers and Informatics 2006
ISBN
80-8073-598-0
Vydavatel
The University of Technology Košice
Místo
Košice
BibTeX
@inproceedings{BUT22271,
  author="Josef {Strnadel}",
  title="On Distribution of Testability Values in Scan-Layout State-Space",
  booktitle="Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics",
  year="2006",
  pages="308--313",
  publisher="The University of Technology Košice",
  address="Košice",
  isbn="80-8073-598-0",
  url="https://www.fit.vut.cz/research/publication/8181/"
}
Soubory
Projekty
Moderní metody syntézy číslicových systémů, GAČR, Standardní projekty, GA102/04/0737, zahájení: 2004-01-01, ukončení: 2006-12-31, ukončen
Optimalizační postupy v diagnostice číslicových systémů, GAČR, Postdoktorandské granty, GP102/05/P193, zahájení: 2005-01-01, ukončení: 2007-12-31, ukončen
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