Detail výsledku

Time- and Space-Efficient Evaluation of Sparse Boolean Functions in Embedded Software

DVOŘÁK, V. Time- and Space-Efficient Evaluation of Sparse Boolean Functions in Embedded Software. Proceedings of 14th Annual IEEE International Conference and Workshops on the Engineering of Computer-Based Systems. Los Alamitos: IEEE Computer Society, 2007. p. 178-185. ISBN: 0-7695-2772-8.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Dvořák Václav, prof. Ing., DrSc., UPSY (FIT)
Abstrakt

The paper addresses software implementation of large sparse systems of Boolean functions. Fast evaluation of such functions with the smallest memory consumption is often required in embedded systems. A new heuristic method of obtaining compact representation of sparse Boolean functions in a form of linked tables is described that can be used for BDD minimization as well. Evaluation of Boolean functions reduces to multiple indirect memory accesses. The method is compared to other techniques like a walk through a BDD or a list search and is illustrated on examples. The presented method is flexible in making trade-offs between performance and memory consumption and may be thus useful for embedded microprocessor or microcontroller software.

Klíčová slova

Multiple-output Boolean functions, software implementation, linked tables, LUT cascades,  heuristic BDD minimization

Rok
2007
Strany
178–185
Sborník
Proceedings of 14th Annual IEEE International Conference and Workshops on the Engineering of Computer-Based Systems
Konference
14th IEEE Conference and Workshop on Engineering of Computer Based Systems
ISBN
0-7695-2772-8
Vydavatel
IEEE Computer Society
Místo
Los Alamitos
BibTeX 
@inproceedings{BUT28595,
  author="Václav {Dvořák}",
  title="Time- and Space-Efficient Evaluation of Sparse Boolean Functions in Embedded Software",
  booktitle="Proceedings of 14th Annual IEEE International Conference and Workshops on the Engineering of Computer-Based Systems",
  year="2007",
  pages="178--185",
  publisher="IEEE Computer Society",
  address="Los Alamitos",
  isbn="0-7695-2772-8",
  url="https://www.fit.vut.cz/research/publication/8324/"
}
Soubory
Projekty
Návrh a obvodová realizace zařízení pro automatické generování patentovatelných invencí, GAČR, Standardní projekty, GA102/07/0850, zahájení: 2007-01-01, ukončení: 2009-12-31, ukončen
Výzkum informačních technologií z hlediska bezpečnosti, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, zahájení: 2007-01-01, ukončení: 2013-12-31, řešení
Výzkumné skupiny
Výzkumná skupina Superpočítačových technologií SC@FIT (VZ SC@FIT)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru