Detail výsledku
Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs
Kaštil Jan, Ing., Ph.D., UIFS (FIT), UPSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., UPSY (FIT), UTKO (FEKT)
Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components.
fault tolerant, on-line checker, architecture, triple modular redundancy, duplex, FPGA, partial reconfiguration
Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components.
@inproceedings{BUT34646,
author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek}",
title="Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs",
booktitle="Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010",
year="2010",
pages="173--176",
publisher="IEEE Computer Society",
address="Wien",
isbn="978-1-4244-6610-8"
}Matematické a inženýrské metody pro vývoj spolehlivých a bezpečných paralelních a distribuovaných počítačových systémů, GAČR, Doktorské granty, GD102/09/H042, zahájení: 2009-01-30, ukončení: 2012-12-31, ukončen
Výzkum informačních technologií z hlediska bezpečnosti, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, zahájení: 2007-01-01, ukončení: 2013-12-31, řešení
Zvyšování spolehlivost a provozuschopnosti v obvodech SoC, GAČR, Standardní projekty, GA102/09/1668, zahájení: 2009-01-01, ukončení: 2011-12-31, ukončen