Detail výsledku

Design Methodology of Configurable High Performance Packet Parser for FPGA

PUŠ, V.; KEKELY, L.; KOŘENEK, J. Design Methodology of Configurable High Performance Packet Parser for FPGA. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014. p. 189-194. ISBN: 978-1-4799-4558-0.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Puš Viktor, Ing., Ph.D.
Kekely Lukáš, Ing., Ph.D., UPSY (FIT)
Kořenek Jan, doc. Ing., Ph.D., UPSY (FIT)
Abstrakt

Packet parsing is among basic operations that are performed at all points of a network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules. However, high-speed parsers often use a significant amount of hardware resources. We propose a novel architecture of a pipelined packet parser for FPGA, which offers low latency in addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput and chip area can be finely tuned to fit the needs of a particular application. The parser is hand-optimized thanks to a direct implementation in VHDL, yet the structure is uniform and easily extensible for new protocols.

Klíčová slova

Packet Parsing, Latency, FPGA

Rok
2014
Strany
189–194
Sborník
17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
Konference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2014
ISBN
978-1-4799-4558-0
Vydavatel
IEEE Computer Society
Místo
Warszawa
DOI
10.1109/DDECS.2014.6868788
UT WoS
000346734200038
EID Scopus
2-s2.0-84938775192
BibTeX 
@inproceedings{BUT111580,
  author="Viktor {Puš} and Lukáš {Kekely} and Jan {Kořenek}",
  title="Design Methodology of Configurable High Performance Packet Parser for FPGA",
  booktitle="17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems",
  year="2014",
  pages="189--194",
  publisher="IEEE Computer Society",
  address="Warszawa",
  doi="10.1109/DDECS.2014.6868788",
  isbn="978-1-4799-4558-0",
  url="https://www.fit.vut.cz/research/publication/10616/"
}
Soubory
Projekty
Architektury paralelních a vestavěných počítačových systémů, VUT, Vnitřní projekty VUT, FIT-S-14-2297, zahájení: 2014-01-01, ukončení: 2016-12-31, ukončen
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, zahájení: 2011-01-01, ukončení: 2015-12-31, ukončen
Výzkumné skupiny
Výzkumná skupina akcelerovaných síťových technologií (VZ ANT)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru