Detail výsledku

The First Circuits Evolved in a Physical Virtual Reconfigurable Device

FRIEDL, Š.; SEKANINA, L. The First Circuits Evolved in a Physical Virtual Reconfigurable Device. Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Bratislava: Slovak Academy of Science, 2004. p. 35-42. ISBN: 80-969117-9-1.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Friedl Štěpán, Ing., FIT (FIT), UPSY (FIT)
Sekanina Lukáš, prof. Ing., Ph.D., UPSY (FIT)
Abstrakt

This paper presents an alternative approach to designing complete evolvable systems on a single FPGA. The proposed strategy utilizes a virtual reconfigurable circuit and hardware implementation of the evolutionary algorithm. Using the evolvable system we have evolved various implementations of the 3x3-bit pipelined multipliers in a few seconds - the first circuits evolved in a physical reconfigurable device in the Czech Republic.

Klíčová slova

evolvable hardware, evolutionary design, FPGA, IP core

Rok
2004
Strany
35–42
Sborník
Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Konference
The 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
ISBN
80-969117-9-1
Vydavatel
Slovak Academy of Science
Místo
Bratislava
BibTeX 
@inproceedings{BUT16922,
  author="Štěpán {Friedl} and Lukáš {Sekanina}",
  title="The First Circuits Evolved in a Physical Virtual Reconfigurable Device",
  booktitle="Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems",
  year="2004",
  pages="35--42",
  publisher="Slovak Academy of Science",
  address="Bratislava",
  isbn="80-969117-9-1"
}
Projekty
Metody návrhu aplikací založených na vyvíjejících se obvodech, GAČR, Postdoktorandské granty, GP102/03/P004, zahájení: 2003-01-01, ukončení: 2005-12-31, ukončen
Výzkumné skupiny
Výzkumná skupina Evolvable Hardware (VZ EHW)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru