Detail výsledku

State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System

SZURMAN, K.; MIČULKA, L.; KOTÁSEK, Z. State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System. In 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014. p. 704-707. ISBN: 978-1-4799-5793-4.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Szurman Karel, Ing., Ph.D.
Mičulka Lukáš, Ing., Ph.D.
Kotásek Zdeněk, doc. Ing., CSc., UPSY (FIT), UTKO (FEKT)
Abstrakt

The paper is focused on the state synchronization issue for a fault-tolerant systems implemented into SRAM-based FPGA after repairing of detected failure. Fault-tolerant systems often use HW redundancy to increase their reliability and partial dynamic reconfiguration of FPGA to repair the part of configuration memory with copy of the protected circuit where the failure was detected. In the paper, implemented fault-tolerant system which integrates previously developed reconfiguration controller and CAN bus control system is described. Then, generic architecture for the synchronization is proposed and synchronization methods for given fault-tolerant system are implemented.

Klíčová slova

state synchronization, recovery, partial dynamic reconfiguration, fault tolerance, FPGA, triple modular redundancy, CAN bus control system

Rok
2014
Strany
704–707
Sborník
17th Euromicro Conference on Digital Systems Design
Konference
17th Euromicro Conference on Digital Systems Design: Architectures, Methods and Tools
ISBN
978-1-4799-5793-4
Vydavatel
IEEE Computer Society
Místo
Verona
DOI
10.1109/DSD.2014.103
UT WoS
000358409000100
EID Scopus
2-s2.0-84928783830
BibTeX 
@inproceedings{BUT111642,
  author="Karel {Szurman} and Lukáš {Mičulka} and Zdeněk {Kotásek}",
  title="State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System",
  booktitle="17th Euromicro Conference on Digital Systems Design",
  year="2014",
  pages="704--707",
  publisher="IEEE Computer Society",
  address="Verona",
  doi="10.1109/DSD.2014.103",
  isbn="978-1-4799-5793-4"
}
Projekty
Architektury paralelních a vestavěných počítačových systémů, VUT, Vnitřní projekty VUT, FIT-S-14-2297, zahájení: 2014-01-01, ukončení: 2016-12-31, ukončen
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, zahájení: 2011-01-01, ukončení: 2015-12-31, ukončen
Metodiky pro návrh systémů odolných proti poruchám do rekonfigurovatelných architektur - vývoj, implementace a verifikace, MŠMT, COST CZ (2011-2017), LD12036, zahájení: 2012-03-01, ukončení: 2015-11-30, ukončen
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru