Detail výsledku

Hardware Acceleration of Intrusion Detection Systems for High-Speed Networks

KUČERA, J.; KEKELY, L.; PUŠ, V.; PIECEK, A.; KOŘENEK, J. Hardware Acceleration of Intrusion Detection Systems for High-Speed Networks. In Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems. Ithaca, NY: Association for Computing Machinery, 2018. p. 177-178. ISBN: 978-1-4503-5902-3.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Kučera Jan, Ing., Ph.D., UPSY (FIT)
Kekely Lukáš, Ing., Ph.D., UPSY (FIT)
Puš Viktor, Ing., Ph.D.
Piecek Adam, Ing.
Kořenek Jan, doc. Ing., Ph.D., UPSY (FIT)
Abstrakt

Intrusion Detection Systems (IDS) are among popular technologiesfor securing computer networks. However, theirhigh computational complexity makes it hard to meet performancegoals of modern high-speed networks. This paperaims at an acceleration of IDS by informed packet discarding.Focusing the limited computational resources available toIDS towards only the most relevant parts of incoming trafficand offloading (bypassing) the rest. We show that this controlled(informed) discarding of well-defined traffic portionshelps IDS to achieve better results and compare software andFPGA accelerated discarding implementations.

Klíčová slova

Suricata IDS, high-speed networks, hardware acceleration

Rok
2018
Strany
177–178
Sborník
Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems
Konference
14th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '18)
ISBN
978-1-4503-5902-3
Vydavatel
Association for Computing Machinery
Místo
Ithaca, NY
DOI
10.1145/3230718.3232114
UT WoS
000474465600026
BibTeX 
@inproceedings{BUT155038,
  author="Jan {Kučera} and Lukáš {Kekely} and Viktor {Puš} and Adam {Piecek} and Jan {Kořenek}",
  title="Hardware Acceleration of Intrusion Detection Systems for High-Speed Networks",
  booktitle="Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems",
  year="2018",
  pages="177--178",
  publisher="Association for Computing Machinery",
  address="Ithaca, NY",
  doi="10.1145/3230718.3232114",
  isbn="978-1-4503-5902-3",
  url="https://www.fit.vut.cz/research/publication/11796/"
}
Soubory
Projekty
IT4Innovations excellence in science, MŠMT, Národní program udržitelnosti II, LQ1602, zahájení: 2016-01-01, ukončení: 2020-12-31, ukončen
Výzkumné skupiny
Výzkumná skupina akcelerovaných síťových technologií (VZ ANT)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru