Detail výsledku

Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques

MRÁZEK, V.; SEKANINA, L.; DOBAI, R.; SÝS, M.; ŠVENDA, P. Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2019, vol. 27, no. 12, p. 2734-2744. ISSN: 1063-8210.
Typ
článek v časopise
Jazyk
anglicky
Autoři
Mrázek Vojtěch, Ing., Ph.D., UPSY (FIT)
Sekanina Lukáš, prof. Ing., Ph.D., UPSY (FIT)
Dobai Roland, Ing., Ph.D., UPSY (FIT)
Sýs Marek
Švenda Petr
Abstrakt

Randomness testing is an important procedure that bit streams, produced by critical cryptographic primitives such as encryption functions and hash functions, have to undergo. In this paper, a new hardware platform for randomness testing is proposed. The platform exploits the principles of genetic programming, which is a machine learning technique developed for automated program and circuit design. The platform is capable of evolving efficient randomness distinguishers directly on a chip. Each distinguisher is represented as a Boolean polynomial in the Algebraic Normal Form. Randomness testing is conducted for bit streams that are either stored in an on-chip memory or generated by a circuit placed on the chip. The platform is developed with a Xilinx Zynq-7000 All Programmable System on Chip which integrates a field programmable gate array with on-chip ARM processors. The platform is evaluated in terms of the quality of randomness testing, performance and resources utilization. With power budget less than 3 W, the platform provides comparable randomness testing capabilities with the standard testing batteries running on a personal computer.

Klíčová slova

randomness testing, evolvable hardware, FPGA

Rok
2019
Strany
2734–2744
Časopis
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, roč. 27, č. 12, ISSN 1063-8210
DOI
UT WoS
000508360300004
EID Scopus
BibTeX
@article{BUT161411,
  author="Vojtěch {Mrázek} and Lukáš {Sekanina} and Roland {Dobai} and Marek {Sýs} and Petr {Švenda}",
  title="Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques",
  journal="IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS",
  year="2019",
  volume="27",
  number="12",
  pages="2734--2744",
  doi="10.1109/TVLSI.2019.2923848",
  issn="1063-8210",
  url="https://www.fit.vut.cz/research/publication/11687/"
}
Soubory
Projekty
Rozvoj kryptoanalytických metod prostřednictvím evolučních výpočtů, GAČR, Standardní projekty, GA16-08565S, zahájení: 2016-01-01, ukončení: 2018-12-31, ukončen
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