Detail výsledku

International Symposium on Design and Diagnostics of Electronic Circuits and Systems

STAMENKOVIC, Z.; BOSIO, A.; CSEREY, G.; NOVÁK, O.; PLESKACZ, W.; SEKANINA, L.; STEININGER, A.; STOJANOVIC, G.; STOPJAKOVÁ, V. International Symposium on Design and Diagnostics of Electronic Circuits and Systems. In 2019 IEEE International Test Conference. Washington, DC: Institute of Electrical and Electronics Engineers, 2019. p. 1-4. ISBN: 978-1-7281-4823-6.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
STAMENKOVIC, Z.
BOSIO, A.
CSEREY, G.
Novák Ondřej, prof.Ing., CSc.
PLESKACZ, W.
Sekanina Lukáš, prof. Ing., Ph.D., UPSY (FIT)
Steininger Andreas, Prof. Dr.
STOJANOVIC, G.
Stopjaková Viera, prof. Ing., Ph.D.
Abstrakt

The paper is a contribution to the 50th anniversary celebration of the International Test Conference (ITC) and its Global Test Forum (GTF), which honors the geographic breadth of the test community and highlights the global reach of ITC during the past 50 years. It covers the past, present, and future of the International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), a symposium which belongs to prominent test technology related events initiated and supported by the ITC.

Klíčová slova

symposium, DDECS, electronics, circuits, systems

Rok
2019
Strany
1–4
Sborník
2019 IEEE International Test Conference
Konference
IEEE International Test Conference
ISBN
978-1-7281-4823-6
Vydavatel
Institute of Electrical and Electronics Engineers
Místo
Washington, DC
DOI
10.1109/ITC44170.2019.9000137
UT WoS
000540385000026
EID Scopus
2-s2.0-85081578342
BibTeX 
@inproceedings{BUT162595,
  author="STAMENKOVIC, Z. and BOSIO, A. and CSEREY, G. and NOVÁK, O. and PLESKACZ, W. and SEKANINA, L. and STEININGER, A. and STOJANOVIC, G. and STOPJAKOVÁ, V.",
  title="International Symposium on Design and Diagnostics of Electronic Circuits and Systems",
  booktitle="2019 IEEE International Test Conference",
  year="2019",
  pages="1--4",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Washington, DC",
  doi="10.1109/ITC44170.2019.9000137",
  isbn="978-1-7281-4823-6",
  url="https://www.fit.vut.cz/research/publication/12200/"
}
Soubory
Projekty
Pokročilé paralelní a vestavěné počítačové systémy, VUT, Vnitřní projekty VUT, FIT-S-17-3994, zahájení: 2017-03-01, ukončení: 2020-02-29, ukončen
Výzkumné skupiny
Výzkumná skupina Evolvable Hardware (VZ EHW)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru