Detail výsledku

High-speed Regular Expression Matching with Pipelined Memory-based Automata

MATOUŠEK, D.; MATOUŠEK, J.; KOŘENEK, J. High-speed Regular Expression Matching with Pipelined Memory-based Automata. Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018. Boulder, CO: IEEE Computer Society, 2018. p. 214-214. ISBN: 978-1-5386-5522-1.
Typ
abstrakt
Jazyk
anglicky
Autoři
Matoušek Denis, Ing., UPSY (FIT)
Matoušek Jiří, Ing., Ph.D., UPSY (FIT)
Kořenek Jan, doc. Ing., Ph.D., UPSY (FIT)
Abstrakt

The paper proposes an architecture of a high-speed regular expression (RE) matching system with fast updates of an RE set. The architecture uses highly memory-efficient Delayed Input DFAs (D 2 FAs), which are organized to a processing pipeline. The architecture is designed so that it communicates only locally among its components in order to achieve high frequency even for a large number of parallel matching engines (MEs), which allows scaling throughput to hundreds of gigabits per second (Gbps). The architecture is able to achieve processing throughput of up to 400 Gbps on current FPGA chips.

Klíčová slova

Regular expression matching, 100 Gbps, 400 Gbps, Delayed Input DFA, Pipelined automata

URL
Rok
2018
Strany
214–214
Kniha
Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018
Konference
The 26th IEEE International Symposium on Field-Programmable Custom Computing Machines
ISBN
978-1-5386-5522-1
Vydavatel
IEEE Computer Society
Místo
Boulder, CO
DOI
10.1109/FCCM.2018.00048
UT WoS
000454742900038
EID Scopus
2-s2.0-85051652311
BibTeX 
@misc{BUT163346,
  author="Denis {Matoušek} and Jiří {Matoušek} and Jan {Kořenek}",
  title="High-speed Regular Expression Matching with Pipelined Memory-based Automata",
  booktitle="Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018",
  year="2018",
  pages="214--214",
  publisher="IEEE Computer Society",
  address="Boulder, CO",
  doi="10.1109/FCCM.2018.00048",
  isbn="978-1-5386-5522-1",
  url="https://ieeexplore.ieee.org/document/8457663",
  note="Abstract"
}
Soubory
Projekty
Pokročilé paralelní a vestavěné počítačové systémy, VUT, Vnitřní projekty VUT, FIT-S-17-3994, zahájení: 2017-03-01, ukončení: 2020-02-29, ukončen
Výzkumné skupiny
Výzkumná skupina akcelerovaných síťových technologií (VZ ANT)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru