Detail výsledku

Novel Logic Circuits Controlled by Vdd

SEKANINA, L.; STAREČEK, L.; KOTÁSEK, Z. Novel Logic Circuits Controlled by Vdd. Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006. p. 85-86. ISBN: 1424401844.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Sekanina Lukáš, prof. Ing., Ph.D., UPSY (FIT)
Stareček Lukáš, Ing., Ph.D., UPSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., UPSY (FIT), UTKO (FEKT)
Abstrakt

Polymorphic gates exhibit one or more additional functions in addition to the main function of the gate. The additional functions can be activated under certain conditions by changing control parameters (such as temperature, Vdd, light etc.) of the circuit. This paper shows a non-trivial polymorphic combinational circuit (5 bit majority/Boolean symmetry) which was designed at the gate level and then simulated using polymorphic NAND/NOR gates controlled by Vdd and some conventional gates at the transistor level. PSpice simulations have shown correct behavior of this circuit.

Klíčová slova

polymorphic gate, logic circuit, evolutionary design

Rok
2006
Strany
85–86
Sborník
Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
Konference
IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
ISBN
1424401844
Vydavatel
IEEE Computer Society
Místo
Praha
BibTeX 
@inproceedings{BUT22240,
  author="Lukáš {Sekanina} and Lukáš {Stareček} and Zdeněk {Kotásek}",
  title="Novel Logic Circuits Controlled by Vdd",
  booktitle="Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop",
  year="2006",
  pages="85--86",
  publisher="IEEE Computer Society",
  address="Praha",
  isbn="1424401844"
}
Projekty
Metody návrhu polymorfních číslicových obvodů, GAČR, Standardní projekty, GA102/06/0599, zahájení: 2006-01-01, ukončení: 2008-12-31, ukončen
Výzkumné skupiny
Výzkumná skupina Evolvable Hardware (VZ EHW)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru