Detail výsledku
Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules
SEKANINA, L.; MARTÍNEK, T.; GAJDA, Z. Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules. 2006 IEEE World Congress on Computational Intelligence. CA: IEEE Computational Intelligence Society, 2006. p. 9676-9683. ISBN: 0-7803-9489-5.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Sekanina Lukáš, prof. Ing., Ph.D., UPSY (FIT)
Martínek Tomáš, doc. Ing., Ph.D., UPSY (FIT)
Gajda Zbyšek, Ing., Ph.D., UPSY (FIT)
Martínek Tomáš, doc. Ing., Ph.D., UPSY (FIT)
Gajda Zbyšek, Ing., Ph.D., UPSY (FIT)
Abstrakt
Multifunctional digital circuits are circuits composed of polymorphic (multifunctional) gates. In addition to its standard logic function (such as NAND), a polymorphic gate exhibits another logic function (such as NOR) which is activated under a specific condition, for example, when Vdd, temperature or illumination reaches a certain level. This paper describes the evolutionary design of multifunctional combinational circuits at the gate level using a circuit simulator and in a field programmable gate array (FPGA). The FPGA-based implementation exhibits a significant speedup against a highly optimized software simulator.
Klíčová slova
polymorphic gate, evolutionary design, FPGA, evolvable hardware
URL
Rok
2006
Strany
9676–9683
Sborník
2006 IEEE World Congress on Computational Intelligence
Konference
IEEE Congress on Evolutionary Computation
ISBN
0-7803-9489-5
Vydavatel
IEEE Computational Intelligence Society
Místo
CA
BibTeX
@inproceedings{BUT22246,
author="Lukáš {Sekanina} and Tomáš {Martínek} and Zbyšek {Gajda}",
title="Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules",
booktitle="2006 IEEE World Congress on Computational Intelligence",
year="2006",
pages="9676--9683",
publisher="IEEE Computational Intelligence Society",
address="CA",
isbn="0-7803-9489-5",
url="http://www.fit.vutbr.cz/~sekanina/publ/cec06/cec06.pdf"
}
Projekty
Metody návrhu polymorfních číslicových obvodů, GAČR, Standardní projekty, GA102/06/0599, zahájení: 2006-01-01, ukončení: 2008-12-31, ukončen
Výzkumné skupiny
Výzkumná skupina Evolvable Hardware (VZ EHW)
Pracoviště
Ústav počítačových systémů
(UPSY)