Detail výsledku

Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing

KAŠTIL, J.; KOŘENEK, J. Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing. Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Vienna: IEEE Computer Society, 2010. p. 149-152. ISBN: 978-1-4244-6610-8.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Kaštil Jan, Ing., Ph.D., UIFS (FIT), UPSY (FIT)
Kořenek Jan, doc. Ing., Ph.D., UPSY (FIT)
Abstrakt

With the increased amount of data transferred by
computer networks, the amount of the malicious traffic also
increases and therefore it is necessary to protect networks
by security systems such as firewalls and Intrusion Detection
Systems (IDS) operating at multigigabit speeds. Pattern matching
is the time critical operation of current IDS. This paper deals
with the analysis of regular expressions used by modern IDS
to describe malicious traffic. According to our analysis, more
than 64 percent of regular expressions create Deterministic Finite
Automaton (DFA) with less than 20 percent of saturation of
the transition table which allows efficient implementation of
pattern matching into FPGA platform. We propose architecture
for fast pattern matching using perfect hashing suitable for
implementation into FPGA platform. The memory requirements
of presented architecture is closed to the theoretical minimum
for sparse transition tables.

Klíčová slova

Intrusion Detection, Perfect Hashing,hardware acceleration, Deterministic Finite Automata

Anotace

With the increased amount of data transferred by
computer networks, the amount of the malicious traffic also
increases and therefore it is necessary to protect networks
by security systems such as firewalls and Intrusion Detection
Systems (IDS) operating at multigigabit speeds. Pattern matching
is the time critical operation of current IDS. This paper deals
with the analysis of regular expressions used by modern IDS
to describe malicious traffic. According to our analysis, more
than 64 percent of regular expressions create Deterministic Finite
Automaton (DFA) with less than 20 percent of saturation of
the transition table which allows efficient implementation of
pattern matching into FPGA platform. We propose architecture
for fast pattern matching using perfect hashing suitable for
implementation into FPGA platform. The memory requirements
of presented architecture is closed to the theoretical minimum
for sparse transition tables.

Rok
2010
Strany
149–152
Sborník
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010
Konference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2010
ISBN
978-1-4244-6610-8
Vydavatel
IEEE Computer Society
Místo
Vienna
BibTeX 
@inproceedings{BUT35426,
  author="Jan {Kaštil} and Jan {Kořenek}",
  title="Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing",
  booktitle="Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010",
  year="2010",
  pages="149--152",
  publisher="IEEE Computer Society",
  address="Vienna",
  isbn="978-1-4244-6610-8",
  url="https://www.fit.vut.cz/research/publication/9200/"
}
Soubory
Projekty
Bezpečné, spolehlivé a adaptivní počítačové systémy, VUT, Vnitřní projekty VUT, FIT-S-10-1, zahájení: 2010-03-01, ukončení: 2010-12-31, ukončen
Výzkum informačních technologií z hlediska bezpečnosti, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, zahájení: 2007-01-01, ukončení: 2013-12-31, řešení
Výzkumné skupiny
Výzkumná skupina akcelerovaných síťových technologií (VZ ANT)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru