Detail výsledku

VHDL RT Level Parser/Analyser of a Source Code

ZBOŘIL, F. VHDL RT Level Parser/Analyser of a Source Code. Proceedings of the fourth international scientific conference Electronic Computers & Informatics'2000. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2000. p. 150-155. ISBN: 80-88922-25-9.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Zbořil František, doc. Ing., CSc.
Abstrakt

During our research activities in the field of testability analysis it was revealed that it is reasonable to perform the algorithms not on the VHDL source file, but rather on "an useable database" which reflects the structure of the circuit under analysis and the diagnostic features of the elements and connections between them. For this purpose an interface between VHDL source text and the software performing the analysis was defined. The paper deals with a special parser/analyser that accepts a subset of the IEEE Standard 1076 Hardware Description Language oriented to description of digital circuits on RT level of modelling. The parser/analyser produces a special database of four mutually depending files that is suitable for testability analysis.

Klíčová slova

VHDL, RT Level, Testability Analysis

Rok
2000
Strany
150–155
Sborník
Proceedings of the fourth international scientific conference Electronic Computers & Informatics'2000
Konference
The fourth International Scientific Conference Electronic computers & informatics-2000
ISBN
80-88922-25-9
Vydavatel
Faculty of Electrical Engineering and Informatics, University of Technology Košice
Místo
Košice
BibTeX 
@inproceedings{BUT5417,
  author="František {Zbořil}",
  title="VHDL RT Level Parser/Analyser of a Source Code",
  booktitle="Proceedings of the fourth international scientific conference Electronic Computers & Informatics'2000",
  year="2000",
  pages="150--155",
  publisher="Faculty of Electrical Engineering and Informatics, University of Technology Košice",
  address="Košice",
  isbn="80-88922-25-9"
}
Projekty
Metodika a prostředky pro analýzu testovatelnosti digitálních obvodů, GAČR, Standardní projekty, GA102/98/1463, zahájení: 1998-01-01, ukončení: 2006-03-31, ukončen
Výzkumné skupiny
Výzkumná skupina inteligentních systémů (VZ INTSYS)
Výzkumná skupina Superpočítačových technologií SC@FIT (VZ SC@FIT)
Pracoviště
Fakulta informačních technologií (FIT)
Nahoru