Detail výsledku

Evolutionary Design of Approximate Multipliers Under Different Error Metrics

VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Design of Approximate Multipliers Under Different Error Metrics. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warsaw: IEEE Computer Society, 2014. p. 135-140. ISBN: 978-1-4799-4558-0.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Vašíček Zdeněk, doc. Ing., Ph.D., UPSY (FIT)
Sekanina Lukáš, prof. Ing., Ph.D., UPSY (FIT)
Abstrakt


Approximate circuits are digital circuits which are intentionally designed in such a way that the specification is not met in terms of functionality in order to obtain some improvements in power consumption, performance or area, in comparison with fully functional circuits. In this paper, we propose to design approximate circuits using evolutionary design techniques. In particular, different error metrics are utilized to assess the circuit functionality. The proposed method begins with a fully functional circuit which is then intentionally degraded by Cartesian genetic programming (CGP) to obtain a circuit with a predefined error. In the second phase, CGP is used to minimize the number of gates or another error criterion. The effect of various error metrics on the search performance, area and power consumption is evaluated in the task of multiplier design.

Klíčová slova

approximate circuit, multiplier, evolutionary design

Rok
2014
Strany
135–140
Sborník
17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
Konference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2014
ISBN
978-1-4799-4558-0
Vydavatel
IEEE Computer Society
Místo
Warsaw
DOI
10.1109/DDECS.2014.6868777
UT WoS
000346734200027
EID Scopus
2-s2.0-84916891835
BibTeX 
@inproceedings{BUT111522,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="Evolutionary Design of Approximate Multipliers Under Different Error Metrics",
  booktitle="17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems",
  year="2014",
  pages="135--140",
  publisher="IEEE Computer Society",
  address="Warsaw",
  doi="10.1109/DDECS.2014.6868777",
  isbn="978-1-4799-4558-0",
  url="https://www.fit.vut.cz/research/publication/10513/"
}
Soubory
Projekty
Architektury paralelních a vestavěných počítačových systémů, VUT, Vnitřní projekty VUT, FIT-S-14-2297, zahájení: 2014-01-01, ukončení: 2016-12-31, ukončen
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, zahájení: 2011-01-01, ukončení: 2015-12-31, ukončen
Pokročilé metody evolučního návrhu složitých číslicových obvodů, GAČR, Standardní projekty, GA14-04197S, zahájení: 2014-01-01, ukončení: 2016-12-31, ukončen
Výzkumné skupiny
Výzkumná skupina Evolvable Hardware (VZ EHW)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru