Fakulta informačních technologií VUT v Brně

Doc. Ing.

Vašíček Zdeněk

Ph.D.

Docent

+420 54114-1165
vasicek@fit.vut.cz
Kancelář L307

Publikace

  • 2019

    MRÁZEK Vojtěch, VAŠÍČEK Zdeněk, SEKANINA Lukáš, HANIF Muhammad A. a SHAFIQUE Muhammad. ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Denver, 2019, s. 1-8.
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    MRÁZEK Vojtěch, HANIF Muhammad A., VAŠÍČEK Zdeněk, SEKANINA Lukáš a SHAFIQUE Muhammad. autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. In: The 56th Annual Design Automation Conference 2019 (DAC '19). Las Vegas: Association for Computing Machinery, 2019, s. 1-6. ISBN 978-1-4503-6725-7.
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    VAŠÍČEK Zdeněk, MRÁZEK Vojtěch a SEKANINA Lukáš. Automated Circuit Approximation Method Driven by Data Distribution. In: Design, Automation and Test in Europe Conference. Florence: European Design and Automation Association, 2019, s. 96-101. ISBN 978-3-9819263-2-3.
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    SEKANINA Lukáš, VAŠÍČEK Zdeněk a MRÁZEK Vojtěch. Automated Search-Based Functional Approximation for Digital Circuits. Approximate Circuits - Methodologies and CAD. Heidelberg: Springer International Publishing, 2019, s. 175-203. ISBN 978-3-319-99322-5.
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    KOCNOVÁ Jitka a VAŠÍČEK Zdeněk. EA-based refactoring of mapped logic circuits. In: 2019 IEEE International Symposium on Circuits and Systems (ISCAS). Red Hook, NY: IEEE Computer Society Press, 2019, s. 1-5. ISBN 978-1-72810-397-6.
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    KOCNOVÁ Jitka a VAŠÍČEK Zdeněk. Impact of subcircuit selection on the efficiency of CGP-based optimization of gate-level circuits. In: GECCO '19 Proceedings of the Genetic and Evolutionary Computation Conference Companion. New York: Association for Computing Machinery, 2019, s. 377-378. ISBN 978-1-4503-6748-6.
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    ANSARI Mohammad S., MRÁZEK Vojtěch, COCKBURN Bruce F., SEKANINA Lukáš, VAŠÍČEK Zdeněk a HAN Jie. Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, roč. 99, č. 99, s. 12. ISSN 1063-8210.
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    KOCNOVÁ Jitka a VAŠÍČEK Zdeněk. Towards a Scalable EA-based Optimization of Digital Circuits. In: Genetic Programming 22nd European Conference, EuroGP 2019. Cham: Springer International Publishing, 2019, s. 81-97. ISBN 978-3-030-16669-4.
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  • 2018

    ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk a VOJNAR Tomáš. ADAC: Automated Design of Approximate Circuits. In: Proceedings of 30th International Conference on Computer Aided Verification (CAV'18). Oxford, UK: Springer International Publishing, 2018, s. 612-620. ISBN 978-3-319-96145-3.
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    VAŠÍČEK Zdeněk. Bridging the Gap Between Evolvable Hardware and Industry Using Cartesian Genetic Programming. Inspired by Nature. Emergence, Complexity and Computation, Vol. 28. Cham: Springer International Publishing, 2018, s. 39-55. ISBN 978-3-319-67996-9.
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    MRÁZEK Vojtěch, VAŠÍČEK Zdeněk a SEKANINA Lukáš. Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. In: Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems. Edinburgh: Institute of Electrical and Electronics Engineers, 2018, s. 264-271. ISBN 978-1-5386-7753-7.
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    SEKANINA Lukáš, MRÁZEK Vojtěch a VAŠÍČEK Zdeněk. Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. In: 25th IEEE International Conference on Electronics Circuits and Systems (ICECS). Bordeaux: IEEE Circuits and Systems Society, 2018, s. 377-380. ISBN 978-1-5386-9562-3.
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    MRÁZEK Vojtěch a VAŠÍČEK Zdeněk. Evolutionary Design of Large Approximate Adders Optimized for Various Error Criteria. In: Proceedings of the Genetic and Evolutionary Computation Conference Companion (GECCO '18). Kyoto: Association for Computing Machinery, 2018, s. 294-295. ISBN 978-1-4503-5764-7.
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    MRÁZEK Vojtěch, SÝS Marek, VAŠÍČEK Zdeněk, SEKANINA Lukáš a MATYÁŠ Václav. Evolving Boolean Functions for Fast and Efficient Randomness Testing. In: Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '18). Kyoto: Association for Computing Machinery, 2018, s. 1302-1309. ISBN 978-1-4503-5618-3.
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    MRÁZEK Vojtěch, VAŠÍČEK Zdeněk a HRBÁČEK Radek. Role of circuit representation in evolutionary design of energy-efficient approximate circuits. IET Computers & Digital Techniques, roč. 2018, č. 4, s. 139-149. ISSN 1751-8601.
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    MRÁZEK Vojtěch, VAŠÍČEK Zdeněk, SEKANINA Lukáš, JIANG Honglan a HAN Jie. Scalable Construction of Approximate Multipliers with Formally Guaranteed Worst-Case Error. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, roč. 26, č. 11, s. 2572-2576. ISSN 1063-8210.
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    SEKANINA Lukáš, VAŠÍČEK Zdeněk, BOSIO Alberto, TRAIOLA Marcello, RECH Paolo, OLIVEIRA Daniel, FERNANDES Fernando a DI Carlo Stefano. Special Session: How Approximate Computing impacts Verification, Test and Reliability. 2018 IEEE 36th VLSI Test Symposium. San Francisco: IEEE Computer Society, 2018. ISBN 978-1-5386-3774-6.
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  • 2017

    SHAFIQUE Muhammad, HAFIZ Rehan, JAVED Muhammad Usama, ABBAS Sarmad, SEKANINA Lukáš, VAŠÍČEK Zdeněk a MRÁZEK Vojtěch. Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. In: 2017 IEEE Computer Society Annual Symposium on VLSI. Los Alamitos: IEEE Computer Society Press, 2017, s. 627-632. ISBN 978-1-5090-6762-6.
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    SEKANINA Lukáš, VAŠÍČEK Zdeněk a MRÁZEK Vojtěch. Approximate Circuits in Low-Power Image and Video Processing: The Approximate Median Filter. Radioengineering, roč. 26, č. 3, s. 623-632. ISSN 1210-2512.
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    ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk a VOJNAR Tomáš. Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished. In: Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD). Irvine, CA: Institute of Electrical and Electronics Engineers, 2017, s. 416-423. ISBN 978-1-5386-3093-8.
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    MRÁZEK Vojtěch, HRBÁČEK Radek, VAŠÍČEK Zdeněk a SEKANINA Lukáš. EvoApprox8b: Library of Approximate Adders and Multipliers for Circuit Design and Benchmarking of Approximation Methods. In: Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017, s. 258-261. ISBN 978-3-9815370-9-3.
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    MRÁZEK Vojtěch a VAŠÍČEK Zdeněk. Parallel Optimization of Transistor Level Circuits using Cartesian Genetic Programming. In: GECCO Companion '17 Proceedings of the Companion Publication of the 2017 on Genetic and Evolutionary Computation Conference. Berlin: Association for Computing Machinery, 2017, s. 1849-1856. ISBN 978-1-4503-4939-0.
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    VAŠÍČEK Zdeněk. Relaxed equivalence checking: a new challenge in logic synthesis. In: Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems. Dresden: IEEE Computer Society, 2017, s. 1-6. ISBN 978-1-5386-0472-4.
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    VAŠÍČEK Zdeněk, MRÁZEK Vojtěch a SEKANINA Lukáš. Towards Low Power Approximate DCT Architecture for HEVC Standard. In: Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017, s. 1576-1581. ISBN 978-3-9815370-9-3.
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    VAŠÍČEK Zdeněk a MRÁZEK Vojtěch. Trading between Quality and Non-functional Properties of Median Filter in Embedded Systems. Genetic Programming and Evolvable Machines, roč. 18, č. 1, s. 45-82. ISSN 1389-2576.
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  • 2016

    HRBÁČEK Radek, MRÁZEK Vojtěch a VAŠÍČEK Zdeněk. Automatic Design of Approximate Circuits by Means of Multi-Objective Evolutionary Algorithms. In: Proceedings of the 11th International Conference on Design & Technology of Integrated Systems in Nanoscale Era. Istanbul: Istanbul Sehir University, 2016, s. 239-244. ISBN 978-1-5090-0335-8.
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    MRÁZEK Vojtěch a VAŠÍČEK Zdeněk. Automatic Design of Arbitrary-Size Approximate Sorting Networks with Error Guarantee. In: Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016 26rd International Workshop on. Bremen: Institute of Electrical and Electronics Engineers, 2016, s. 221-228. ISBN 978-1-5090-0733-2.
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    MRÁZEK Vojtěch, SARWAR Syed Shakib, SEKANINA Lukáš, VAŠÍČEK Zdeněk a ROY Kaushik. Design of Power-Efficient Approximate Multipliers for Approximate Artificial Neural Networks. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Austin, TX: Association for Computing Machinery, 2016, s. 811-817. ISBN 978-1-4503-4466-1.
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    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Evolutionary Design of Complex Approximate Combinational Circuits. Genetic Programming and Evolvable Machines, roč. 17, č. 2, s. 169-192. ISSN 1389-2576.
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    VAŠÍČEK Zdeněk, MRÁZEK Vojtěch a SEKANINA Lukáš. Evolutionary Functional Approximation of Circuits Implemented into FPGAs. In: 2016 IEEE Symposium Series on Computational Intelligence. Athens: Institute of Electrical and Electronics Engineers, 2016, s. 1-8. ISBN 978-1-5090-4240-1.
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    SEKANINA Lukáš a VAŠÍČEK Zdeněk. Genetic Improvement for Approximate Computing. In: 2nd Workshop on Approximate Computing (WAPCO 2016). Prague, 2016, s. 1-2.
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    VAŠÍČEK Zdeněk. New Methods for Synthesis and Approximation of Logic Circuits. Brno, 2016.
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    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Search-based synthesis of approximate circuits implemented into FPGAs. In: 26th International Conference on Field Programmable Logic and Applications. Lausanne: Institute of Electrical and Electronics Engineers, 2016, s. 1-4. ISBN 978-2-8399-1844-2.
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    HOLÍK Lukáš, LENGÁL Ondřej, ROGALEWICZ Adam, SEKANINA Lukáš, VAŠÍČEK Zdeněk a VOJNAR Tomáš. Towards Formal Relaxed Equivalence Checking in Approximate Computing Methodology. In: 2nd Workshop on Approximate Computing (WAPCO 2016). Prague, 2016, s. 1-6.
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  • 2015

    MRÁZEK Vojtěch a VAŠÍČEK Zdeněk. Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. In: Proceedings of 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing. Porto: Institute of Electrical and Electronics Engineers, 2015, s. 106-113. ISBN 978-1-4673-8299-1.
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    VAŠÍČEK Zdeněk. Cartesian GP in Optimization of Combinational Circuits with Hundreds of Inputs and Thousands of Gates. In: Genetic Programming, 18th European Conference, EuroGP 2015. LCNS 9025. Berlin: Springer International Publishing, 2015, s. 139-150. ISBN 978-3-319-16500-4.
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    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Circuit Approximation Using Single- and Multi-Objective Cartesian GP. In: Genetic Programming. Lecture Notes in Computer Science, roč. 9025. Berlin: Springer International Publishing, 2015, s. 217-229. ISBN 978-3-319-16500-4.
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    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Evolutionary Approach to Approximate Digital Circuits Design. IEEE Transactions on Evolutionary Computation, roč. 19, č. 3, s. 432-444. ISSN 1089-778X.
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    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Evolutionary approximation of complex digital circuits. In: Proceedings of the Companion Publication of the 2015 on Genetic and Evolutionary Computation Conference. New York: Association for Computing Machinery, 2015, s. 1505-1506. ISBN 978-1-4503-3488-4.
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    MRÁZEK Vojtěch, VAŠÍČEK Zdeněk a SEKANINA Lukáš. Evolutionary Approximation of Software for Embedded Systems: Median Function. In: GECCO Companion '15 Proceedings of the Companion Publication of the 2015 on Genetic and Evolutionary Computation Conference. ACM. New York: Association for Computing Machinery, 2015, s. 795-801. ISBN 978-1-4503-3488-4.
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    SEKANINA Lukáš a VAŠÍČEK Zdeněk. Evolutionary Computing in Approximate Circuit Design and Optimization. In: 1st Workshop on Approximate Computing (WAPCO 2015). Amsterdam, 2015, s. 1-6.
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    MRÁZEK Vojtěch a VAŠÍČEK Zdeněk. Evolutionary Design of Transistor Level Digital Circuits using Discrete Simulation. In: Genetic Programming, 18th European Conference, EuroGP 2015. LCNS 9025. Berlin: Springer International Publishing, 2015, s. 66-77. ISBN 978-3-319-16500-4.
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    SEKANINA Lukáš a VAŠÍČEK Zdeněk. Functional Equivalence Checking for Evolution of Complex Digital Circuits. Evolvable Hardware - From Practice to Application. Berlin: Springer Verlag, 2015, s. 175-189. ISBN 978-3-662-44615-7.
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  • 2014

    MRÁZEK Vojtěch a VAŠÍČEK Zdeněk. Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform. In: 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014, s. 9-16. ISBN 978-1-4799-4480-4.
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    SEKANINA Lukáš, PTÁK Ondřej a VAŠÍČEK Zdeněk. Cartesian Genetic Programming as Local Optimizer of Logic Networks. In: 2014 IEEE Congress on Evolutionary Computation. Beijing: IEEE Computational Intelligence Society, 2014, s. 2901-2908. ISBN 978-1-4799-1488-3.
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    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Evolutionary Design of Approximate Multipliers Under Different Error Metrics. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warsaw: IEEE Computer Society, 2014, s. 135-140. ISBN 978-1-4799-4558-0.
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    VAŠÍČEK Zdeněk a SEKANINA Lukáš. How to Evolve Complex Combinational Circuits From Scratch?. In: 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014, s. 133-140. ISBN 978-1-4799-4480-4.
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    BIDLO Michal a VAŠÍČEK Zdeněk. On Evolution of Multi-Category Pattern Classifiers Suitable for Embedded Systems. In: Genetic Programming, 17th European Conference, EuroGP 2014. Lecture Notes in Computer Science, roč. 8599. Berlin: Springer Verlag, 2014, s. 234-245. ISBN 978-3-662-44302-6.
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    SEKANINA Lukáš a VAŠÍČEK Zdeněk. On Evolutionary Approximation of Logic Circuits. Computing with New Resources. Berlin: Springer Verlag, 2014, s. 367-378. ISBN 978-3-319-13349-2.
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  • 2013

    SEKANINA Lukáš a VAŠÍČEK Zdeněk. Approximate Circuit Design by Means of Evolvable Hardware. In: 2013 IEEE International Conference on Evolvable Systems (ICES). Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI). Singapur: IEEE Computer Society, 2013, s. 21-28. ISBN 978-1-4673-5847-7.
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    BIDLO Michal a VAŠÍČEK Zdeněk. Evolution of Cellular Automata with Conditionally Matching Rules. In: 2013 IEEE Congress on Evolutionary Computation (CEC 2013). Cancún: IEEE Computer Society, 2013, s. 1178-1185. ISBN 978-1-4799-0452-5.
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    VAŠÍČEK Zdeněk, BIDLO Michal a SEKANINA Lukáš. Evolution of efficient real-time non-linear image filters for FPGAs. Soft Computing, roč. 17, č. 11, s. 2163-2180. ISSN 1432-7643.
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    BIDLO Michal a VAŠÍČEK Zdeněk. Functional-Level Development of Image Filters by Means of Cellular Automata. In: 2013 IEEE International Conference on Evolvable Systems (ICES). Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI). Singapore: IEEE Computer Society, 2013, s. 29-36. ISBN 978-1-4673-5847-7.
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    SEKANINA Lukáš, RŮŽIČKA Richard, VAŠÍČEK Zdeněk, ŠIMEK Václav a HANÁČEK Petr. Implementing a Unique Chip ID on a Reconfigurable Polymorphic Circuit. Information Technology And Control, roč. 42, č. 1, s. 7-14. ISSN 1392-124X.
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  • 2012

    SEKANINA Lukáš a VAŠÍČEK Zdeněk. A SAT-based Fitness Function for Evolutionary Optimization of Polymorphic Circuits. In: Proc. of the 2012 Design, Automation and Test in Europe. Dresden: European Design and Automation Association, 2012, s. 715-720. ISBN 978-1-4577-2145-8.
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    BIDLO Michal a VAŠÍČEK Zdeněk. Cellular Automaton as Sorting Network Generator Using Instruction-Based Development. Lecture Notes in Computer Science, roč. 2012, č. 7495, s. 214-223. ISSN 0302-9743.
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    VAŠÍČEK Zdeněk a SLANÝ Karel. Efficient Phenotype Evaluation in Cartesian Genetic Programming. In: Proc. of the 15th European Conference on Genetic Programming. Lecture Notes in Computer Science, roč. 7244. Heidelberg: Springer Verlag, 2012, s. 266-278. ISBN 978-3-642-29138-8.
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    BIDLO Michal a VAŠÍČEK Zdeněk. Evolution of Cellular Automata Using Instruction-Based Approach. In: 2012 IEEE World Congress on Computational Intelligence. CA: Institute of Electrical and Electronics Engineers, 2012, s. 1060-1067. ISBN 978-1-4673-1508-1.
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    VAŠÍČEK Zdeněk a SEKANINA Lukáš. On Area Minimization of Complex Combinational Circuits Using Cartesian Genetic Programming. In: 2012 IEEE World Congress on Computational Intelligence. CA: Institute of Electrical and Electronics Engineers, 2012, s. 2379-2386. ISBN 978-1-4673-1508-1.
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    SEKANINA Lukáš, SALAJKA Vojtěch a VAŠÍČEK Zdeněk. Two-Step Evolution of Polymorphic Circuits for Image Multi-Filtering. In: 2012 IEEE World Congress on Computational Intelligence. CA: Institute of Electrical and Electronics Engineers, 2012, s. 432-439. ISBN 978-1-4673-1508-1.
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  • 2011

    VAŠÍČEK Zdeněk a SEKANINA Lukáš. A Global Postsynthesis Optimization Method for Combinational Circuits. In: Proc. of the Design, Automation and Test in Europe DATE 2011. Grenoble: European Design and Automation Association, 2011, s. 1525-1528. ISBN 978-3-9810801-7-9.
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    SEKANINA Lukáš a VAŠÍČEK Zdeněk. CGP Acceleration Using Field-Programmable Gate Arrays. Cartesian Genetic Programming. Natural Computing Series. Berlin: Springer Verlag, 2011, s. 217-230. ISBN 978-3-642-17309-7.
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    VAŠÍČEK Zdeněk, BIDLO Michal, SEKANINA Lukáš a GLETTE Kyrre. Evolutionary Design of Efficient and Robust Switching Image Filters. In: Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2011, s. 192-199. ISBN 978-1-4577-0599-1.
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    VAŠÍČEK Zdeněk a BIDLO Michal. Evolutionary Design of Robust Noise-Specific Image Filters. In: 2011 IEEE Congress on Evolutionary Computation. New Orleans: IEEE Computer Society, 2011, s. 269-276. ISBN 978-1-4244-7834-7.
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    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Evolutionary Optimization of Complex Digital Circuits. In: 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masarykova universita, 2011, s. 1. ISBN 978-80-214-4305-1.
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    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Extensions of Cartesian Genetic Programming for Optimization of Complex Combinational Circuits. In: Proc. of the 20th International Workshop on Logic and Synthesis. San Diego: University of California San Diego, 2011, s. 55-61.
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    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. Genetic Programming and Evolvable Machines, roč. 12, č. 3, s. 305-327. ISSN 1389-2576.
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    JIRÁK Ota, KŘIVKA Zbyněk a VAŠÍČEK Zdeněk. Integrated Development Environment for Virtual Laboratory. In: International Technology, Education and Development Conference. Valencia: International Association for Technology, Education and Development, 2011, s. 10. ISBN 978-84-614-7423-3.
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    KŘIVKA Zbyněk a VAŠÍČEK Zdeněk. The Virtualization of Development Boards in the Virtual Laboratory of Microprocessor Technology. In: 12th International Carpathian Control Conference (ICCC). Velké Karlovice: VŠB Technická univerzita Ostrava, 2011, s. 424-428. ISBN 978-1-61284-359-9.
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    DULÍK Tomáš, KŘIVKA Zbyněk, KADLEC Jiří, BLIŽŇÁK Michal, BUDÍKOVÁ Věra, JIRÁK Ota, OLŠAROVÁ Nela, TRBUŠEK Josef a VAŠÍČEK Zdeněk. Virtuální laboratoř pro vývoj aplikací s mikroprocesory a FPGA. Brno: Akademické nakladatelství CERM sro., 2011. ISBN 978-80-7204-754-3.
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  • 2010

    VAŠÍČEK Zdeněk, SEKANINA Lukáš a BIDLO Michal. A Method for Design of Impulse Bursts Noise Filters Optimized for FPGA Implementations. In: DATE 2010: Design, Automation and Test in Europe. Dresden: European Design and Automation Association, 2010, s. 1731-1736. ISBN 978-3-9810801-6-2.
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    JIRÁK Ota, KŘIVKA Zbyněk a VAŠÍČEK Zdeněk. Component Interconnection Inference Tool Supporting the Design of Small FPGA-based Embedded Systems. In: Proceedings of the IADIS International Conference Applied Computing 2010. Timisoara: International Association for Development of the Information Society, 2010, s. 230-234. ISBN 978-972-8939-30-4.
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    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units. Computing and Informatics, roč. 29, č. 6, s. 1359-1371. ISSN 1335-9150.
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    JIRÁK Ota, KŘIVKA Zbyněk, OLŠAROVÁ Nela a VAŠÍČEK Zdeněk. Odvozování propojení komponent pro podporu návrhu pro malé FPGA čipy. In: DATAKON 2010 Proceedings (Ed. Petr Šaloun). Mikulov: Ostravská univerzita, 2010, s. 81-90. ISBN 978-80-7368-424-2.
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    FIŠER Petr, SCHMIDT Jan, VAŠÍČEK Zdeněk a SEKANINA Lukáš. On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming. In: Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010, s. 346-351. ISBN 978-1-4244-6610-8.
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    BIDLO Michal, SLANÝ Karel a VAŠÍČEK Zdeněk. Sorting Network Development Using Cellular Automata. In: Evolvable Systems: From Biology to Hardware. 9th International Conference, ICES 2010, York, UK, September 6-8, 2010, Proceedings, LNCS 6274. London: Springer London, 2010, s. 85-96. ISBN 978-3-642-15322-8.
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    VAŠÍČEK Zdeněk. Využití a akcelerace evolučních technik pro návrh číslicových obvodů. In: Počítačové architektury a diagnostika 2010. Brno: Fakulta informačních technologií VUT v Brně, 2010, s. 165-170. ISBN 978-80-214-4140-8.
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  • 2009

    BIDLO Michal a VAŠÍČEK Zdeněk. Comparison of the Uniform and Non-Uniform Cellular Automata-Based Approach to the Development of Combinational Circuits. In: Proceedings 2009 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2009, s. 423-430. ISBN 978-0-7695-3714-6.
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    BIDLO Michal a VAŠÍČEK Zdeněk. Development of Combinational Circuits Using Non-Uniform Cellular Automata: Initial Results. In: Genetic and Evolutionary Computation. New York: Association for Computing Machinery, 2009, s. 1839-1840. ISBN 978-1-60558-325-9.
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    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Efficient Hardware Accelerator for Symbolic Regression Problems. In: 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masarykova universita, 2009, s. 192-199. ISBN 978-80-87342-04-6.
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    SEKANINA Lukáš, VAŠÍČEK Zdeněk, RŮŽIČKA Richard, BIDLO Michal, JAROŠ Jiří a ŠVENDA Petr. Evoluční hardware: Od automatického generování patentovatelných invencí k sebemodifikujícím se strojům. Edice Gerstner. Praha: Nakladatelství Academia, 2009. ISBN 978-80-200-1729-1.
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    VAŠÍČEK Zdeněk, BIDLO Michal, SEKANINA Lukáš, TORRESEN Jim, GLETTE Kyrre a FURUHOLMEN Marcus. Evolution of Impulse Bursts Noise Filters. In: Proc. of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2009, s. 27-34. ISBN 978-0-7695-3714-6.
    Detail

    BIDLO Michal a VAŠÍČEK Zdeněk. Investigating Gate-Level Evolutionary Development of Combinational Multipliers Using Enhanced Cellular Automata-Based Model. In: Proc. of 2009 IEEE Congress on Evolutionary Computation. NA: IEEE Computational Intelligence Society, 2009, s. 2241-2248. ISBN 978-1-4244-2958-5.
    Detail

    SEKANINA Lukáš, RŮŽIČKA Richard, VAŠÍČEK Zdeněk, PROKOP Roman a FUJCIK Lukáš. REPOMO32 - New Reconfigurable Polymorphic Integrated Circuit for Adaptive Hardware. In: Proc. of the 2009 IEEE Symposium Series on Computational Intelligence - Workshop on Evolvable and Adaptive Hardware. Nashville: IEEE Computational Intelligence Society, 2009, s. 39-46. ISBN 978-1-4244-2755-0.
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  • 2008

    VAŠÍČEK Zdeněk. Adaptivní hardware na bázi vyvíjejících se obvodů. In: Počítačové architektury a diagnostika 2008. Česko-slovenský seminář pro studenty doktorandského studia. Liberec: Technická univerzita v Liberci, 2008, s. 119-124. ISBN 978-80-7372-378-1.
    Detail

    VAŠÍČEK Zdeněk, ČAPKA Ladislav a SEKANINA Lukáš. Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit. In: Proc. of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2008, s. 3-10. ISBN 978-0-7695-3166-3.
    Detail

    ŠIMEK Václav, VAŠÍČEK Zdeněk a SLANÝ Karel. Can the performance of GPGPU really beat CPU in evolutionary design task?. In: 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masarykova universita, 2008, s. 264-264. ISBN 978-80-7355-082-0.
    Detail

    BIDLO Michal a VAŠÍČEK Zdeněk. Cellular Automata-Based Development of Combinational and Polymorphic Circuits: A Comparative Study. In: Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science, roč. 5216. Berlin: Springer Verlag, 2008, s. 106-117. ISBN 978-3-540-85856-0.
    Detail

    JIRÁK Ota, KŘIVKA Zbyněk a VAŠÍČEK Zdeněk. Debugging of Small FPGA-Based Embedded System. In: Proceedings of ASIS 2008. Ostrava: MARQ, 2008, s. 6. ISBN 978-80-86840-42-0.
    Detail

    BIDLO Michal a VAŠÍČEK Zdeněk. Gate-Level Evolutionary Development Using Cellular Automata. In: 2008 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society Press, 2008, s. 11-18. ISBN 978-0-7695-3166-3.
    Detail

    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Hardware Accelerators for Cartesian Genetic Programming. In: Eleventh European Conference on Genetic Programming. Lecture Notes in Computer Science, roč. 4971. Berlin: Springer Verlag, 2008, s. 230-241. ISBN 978-3-540-78670-2.
    Detail

    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Novel Hardware Implementation of Adaptive Median Filters. In: Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008, s. 110-115. ISBN 978-1-4244-2276-0.
    Detail

    VAŠÍČEK Zdeněk, ŽÁDNÍK Martin, SEKANINA Lukáš a TOBOLA Jiří. On Evolutionary Synthesis of Linear Transforms in FPGA. In: Evolvable Systems: From Biology > to > Hardware. Lecture Notes in Computer Science, roč. 5216. Berlin: Springer Verlag, 2008, s. 141-152. ISBN 978-3-540-85856-0.
    Detail

    VAŠÍČEK Zdeněk. Towards Automatic Design of Competitive Image Filters in FPGAs. In: Proceedings of Junior Scientist Conference 2008. Vienna: Technische Universität Wien, 2008, s. 2. ISBN 978-3-200-01612-5.
    Detail

  • 2007

    VAŠÍČEK Zdeněk a SEKANINA Lukáš. An Area-Efficient Alternative to Adaptive Median Filtering in FPGAs. In: Proc. of 2007 International Conference on Field Programmable Logic and Applications. Los Alamitos: IEEE Computer Society, 2007, s. 216-221. ISBN 1424410606.
    Detail

    VAŠÍČEK Zdeněk a SEKANINA Lukáš. An Evolvable Hardware System in Xilinx Virtex II Pro FPGA. International Journal of Innovative Computing and Applications, roč. 1, č. 1, s. 63-73. ISSN 1751-648X.
    Detail

    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Evaluation of a New Platform For Image Filter Evolution. In: Proc. of the 2007 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2007, s. 577-584. ISBN 076952866X.
    Detail

    DRAHANSKÝ Martin a VAŠÍČEK Zdeněk. Image stabilization in a video-stream. IDET 2007, Brno: EVPÚ Defence, s.r.o., 2007.
    Detail

    ČAPKA Ladislav a VAŠÍČEK Zdeněk. Investigating the Influence of Mutation Operators in Cartesian Genetic Programming. In: 13th International Conference on Soft Computing. Brno: Fakulta strojního inženýrství VUT, 2007, s. 43-47. ISBN 978-80-214-3473-8.
    Detail

    VAŠÍČEK Zdeněk. Reálné aplikace evolučního návrhu. In: Počítačové architektury a diagnostika 2007. Česko-slovenský seminář pro studenty doktorandského studia. Plzeň: Západočeská univerzita v Plzni, 2007, s. 137-142. ISBN 978-80-7043-605-9.
    Detail

    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Reducing the Area on a Chip Using a Bank of Evolved Filters. In: Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science, roč. 4684. Berlin: Springer Verlag, 2007, s. 222-232. ISBN 978-3-540-74625-6.
    Detail

  • 2006

    SEKANINA Lukáš a VAŠÍČEK Zdeněk. On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level. In: Applications of Evolutionary Computing. Lecture Notes in Computer Science, roč. 3907. Berlin: Springer Verlag, 2006, s. 344-355. ISBN 978-3-540-33237-4.
    Detail

  • 2004

    VAŠÍČEK Zdeněk a SEKANINA Lukáš. Evoluční návrh kombinačních obvodů. Elektrorevue - www.elektrorevue.cz, roč. 2004, č. 43, s. 1-6. ISSN 1213-1539.
    Detail

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