Výzkumná skupina Spolehlivé číslicové systémy

2023

LOJDA Jakub, PÁNEK Richard, SEKANINA Lukáš a KOTÁSEK Zdeněk. Automated Design and Usage of the Fault-Tolerant Dynamic Partial Reconfiguration Controller for FPGAs. Microelectronics Reliability, roč. 2023, č. 144, s. 1-16. ISSN 0026-2714.
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PÁNEK Richard a LOJDA Jakub. The Fault-tolerant Single-FPGA Systems with a Self-repair Reconfiguration Controller. In: LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings. Quito: Institute of Electrical and Electronics Engineers, 2023, s. 104-107. ISBN 978-1-6654-5705-7.
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2022

STRNADEL Josef. Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking. In: Proceedings of 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Prague: Institute of Electrical and Electronics Engineers, 2022, s. 88-93. ISBN 978-1-6654-9431-1.
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2021

STRNADEL Josef. Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults. In: Proceedings of 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Vienna: Institute of Electrical and Electronics Engineers, 2021, s. 111-114. ISBN 978-1-6654-3595-6.
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LOJDA Jakub, PÁNEK Richard a KOTÁSEK Zdeněk. Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs. In: Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021. Palermo: Institute of Electrical and Electronics Engineers, 2021, s. 549-552. ISBN 978-1-6654-2703-6.
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PÁNEK Richard, LOJDA Jakub, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Reliability Analysis of the FPGA Control System with Reconfiguration Hardening. In: Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021. Palermo: Institute of Electrical and Electronics Engineers, 2021, s. 553-556. ISBN 978-1-6654-2703-6.
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LOJDA Jakub, PÁNEK Richard, PODIVÍNSKÝ Jakub, ČEKAN Ondřej, KRČMA Martin a KOTÁSEK Zdeněk. Testing Embedded Software Through Fault Injection: Case Study on Smart Lock. In: 2021 IEEE 22nd Latin American Test Symposium, LATS 2021. Punta del Este: Institute of Electrical and Electronics Engineers, 2021, s. 80-85. ISBN 978-1-6654-2057-0.
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LOJDA Jakub, PODIVÍNSKÝ Jakub, ČEKAN Ondřej a KOTÁSEK Zdeněk. Accelerating Tests of Arithmetic Circuits Through On-FPGA Stimuli Generation and Their Reduction. In: International Conference on Electrical, Computer, Communications and Mechatronics Engineering, ICECCME 2021. Mauritius: Institute of Electrical and Electronics Engineers, 2021, s. 1628-1633. ISBN 978-1-6654-1262-9.
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LOJDA Jakub, PÁNEK Richard a KOTÁSEK Zdeněk. Automatically-Designed Fault-Tolerant Systems: Failed Partitions Recovery. In: 2021 IEEE East-West Design and Test Symposium, EWDTS 2021 - Proceedings. Batumi: Institute of Electrical and Electronics Engineers, 2021, s. 26-33. ISBN 978-1-6654-4503-0.
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2020

STRNADEL Josef. Statistical Model Checking of Approximate Circuits: Challenges and Opportunities. In: Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). Grenoble: IEEE Computer Society, 2020, s. 1574-1577. ISBN 978-3-9819263-4-7.
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PODIVÍNSKÝ Jakub, LOJDA Jakub, PÁNEK Richard, ČEKAN Ondřej, KRČMA Martin a KOTÁSEK Zdeněk. Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks. In: 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS). San José: IEEE Circuits and Systems Society, 2020, s. 1-4. ISBN 978-1-7281-3427-7.
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LOJDA Jakub, PODIVÍNSKÝ Jakub, ČEKAN Ondřej, PÁNEK Richard, KRČMA Martin a KOTÁSEK Zdeněk. Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. In: Proceedings - 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020. Novi Sad: Institute of Electrical and Electronics Engineers, 2020, s. 1-4. ISBN 978-1-7281-9938-2.
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PÁNEK Richard, LOJDA Jakub, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study. In: 2020 International Symposium on VLSI Design, Automation, and Test (VLSI-DAT) : proceedings of technical papers. Hsinchu: IEEE Computer Society, 2020, s. 121-124. ISBN 978-1-7281-6083-2.
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LOJDA Jakub, PÁNEK Richard, PODIVÍNSKÝ Jakub, ČEKAN Ondřej, KRČMA Martin a KOTÁSEK Zdeněk. Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. In: Proceedings - Euromicro Conference on Digital System Design, DSD 2020. Kranj: Institute of Electrical and Electronics Engineers, 2020, s. 680-683. ISBN 978-1-7281-9535-3.
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LOJDA Jakub, PÁNEK Richard, PODIVÍNSKÝ Jakub, ČEKAN Ondřej, KRČMA Martin a KOTÁSEK Zdeněk. Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock. In: 2020 IEEE East-West Design and Test Symposium, EWDTS 2020 - Proceedings. Varna: Institute of Electrical and Electronics Engineers, 2020, s. 24-28. ISBN 978-1-7281-9899-6.
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2019

STRNADEL Josef. Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates. In: Design, Automation & Test in Europe Conference & Exhibition (DATE). Florence: IEEE Computer Society, 2019, s. 614-617. ISBN 978-3-9819263-2-3.
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PODIVÍNSKÝ Jakub, LOJDA Jakub a KOTÁSEK Zdeněk. Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019, s. 97-100. ISBN 978-1-7281-1756-0.
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LOJDA Jakub, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019, s. 93-96. ISBN 978-1-7281-1756-0.
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KRČMA Martin, KOTÁSEK Zdeněk a LOJDA Jakub. Detecting hard synapses faults in artificial neural networks. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago de Chile: IEEE Computer Society, 2019, s. 1-6. ISBN 978-1-7281-1756-0.
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SZURMAN Karel a KOTÁSEK Zdeněk. Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019, s. 32-35. ISBN 978-1-7281-1756-0.
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SZURMAN Karel a KOTÁSEK Zdeněk. Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor neo430. In: 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019). Cluj-Napoca: IEEE Computer Society, 2019, s. 136-140. ISBN 978-1-7281-0073-9.
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ČEKAN Ondřej, PODIVÍNSKÝ Jakub, LOJDA Jakub, PÁNEK Richard, KRČMA Martin a KOTÁSEK Zdeněk. Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. In: Proceedings of the 2019 22nd Euromicro Conference on Digital System Design. Kalithea: Institute of Electrical and Electronics Engineers, 2019, s. 506-513. ISBN 978-1-7281-2861-0.
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ČEKAN Ondřej, PODIVÍNSKÝ Jakub, LOJDA Jakub, PÁNEK Richard, KRČMA Martin a KOTÁSEK Zdeněk. Smart Electronic Locks and Their Reliability. In: Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy: České vysoké učení technické, 2019, s. 4-5. ISBN 978-80-01-06607-2.
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SZURMAN Karel a KOTÁSEK Zdeněk. Fault Recovery for Coarse-Grained TMR Soft-Core Processor Using Partial Reconfiguration and State Synchronization. In: Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy: Fakulta informačních technologií ČVUT, 2019, s. 6-7. ISBN 978-80-01-06607-2.
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2018

STRNADEL Josef. Predictability Analysis of Interruptible Systems by Statistical Model Checking. IEEE Design & Test, roč. 35, č. 2, 2018, s. 57-63. ISSN 2168-2356.
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LOJDA Jakub, PODIVÍNSKÝ Jakub, KOTÁSEK Zdeněk a KRČMA Martin. Majority Type and Redundancy Level Influences on Redundant Data Types Approach for HLS. In: 2018 16th Biennial Baltic Electronics Conference (BEC). Tallinn: IEEE Computer Society, 2018, s. 1-4. ISBN 978-1-5386-7312-6.
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PODIVÍNSKÝ Jakub, LOJDA Jakub a KOTÁSEK Zdeněk. FPGA-based Robot Controller: An Experimental Evaluation of Fault Tolerance Properties. In: INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť, 2018, s. 9-12.
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ČEKAN Ondřej a KOTÁSEK Zdeněk. Random Test Generation Through a Probabilistic Constrained Grammar. In: INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť, 2018, s. 5-8.
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STRNADEL Josef. Statistical Model Checking of Processor Systems in Various Interrupt Scenarios. In: Proceedings of 8th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation (ISoLA). Lecture Notes in Computer Science, Vol. 11245. Cham: Springer International Publishing, 2018, s. 414-429. ISSN 0302-9743.
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PODIVÍNSKÝ Jakub, ČEKAN Ondřej, KRČMA Martin, BURGET Radek, HRUŠKA Tomáš a KOTÁSEK Zdeněk. A Processor Optimization Framework for a Selected Application. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, s. 564-574. ISBN 978-1-5386-5710-2.
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PODIVÍNSKÝ Jakub, LOJDA Jakub, ČEKAN Ondřej a KOTÁSEK Zdeněk. Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. In: Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018, s. 229-236. ISBN 978-1-5386-7376-8.
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LOJDA Jakub, PODIVÍNSKÝ Jakub, ČEKAN Ondřej, PÁNEK Richard a KOTÁSEK Zdeněk. FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant Systems Design Automation. In: Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018, s. 244-251. ISBN 978-1-5386-7376-8.
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ČEKAN Ondřej, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Program Generation Through a Probabilistic Constrained Grammar. In: Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018. Praha: IEEE Computer Society, 2018, s. 214-220. ISBN 978-1-5386-7376-8.
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LOJDA Jakub a KOTÁSEK Zdeněk. Fault Tolerance in HLS for the Purposes of Reliable System Design Automation. In: Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: Fakulta informačních technologií ČVUT, 2018, s. 31-32. ISBN 978-80-01-06456-6.
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PODIVÍNSKÝ Jakub, LOJDA Jakub a KOTÁSEK Zdeněk. An Experimental Evaluation of Fault-Tolerant FPGA-based Robot Controller. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, s. 63-69. ISBN 978-1-5386-5710-2.
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PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. In: Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: České vysoké učení technické, 2018, s. 33-34. ISBN 978-80-01-06456-6.
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LOJDA Jakub, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, s. 80-86. ISBN 978-1-5386-5710-2.
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PÁNEK Richard, LOJDA Jakub, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. In: Proceedings of IEEE East-West Design & Test Symposium. Kazaň: IEEE Computer Society, 2018, s. 129-134. ISBN 978-1-5386-5710-2.
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LOJDA Jakub a KOTÁSEK Zdeněk. Automatizace návrhu spolehlivých systémů a její dílčí komponenty. In: Počítačové architektury & diagnostika 2018. Stachy: Západočeská univerzita v Plzni, 2018, s. 5-8. ISBN 978-80-261-0814-6.
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PÁNEK Richard. Metodika návrhu řadiče rekonfigurace pro Systémy odolné proti poruchám. In: Počítačové architektury & diagnostika 2018. Stachy: Západočeská univerzita v Plzni, 2018, s. 21-24. ISBN 978-80-261-0814-6.
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ČEKAN Ondřej, PÁNEK Richard a KOTÁSEK Zdeněk. Input and Output Generation for the Verification of ALU: a Use Case. In: Proceedings of 2018 IEEE East-West Design and Test Symposium, EWDTS 2018. Kazan: IEEE Computer Society, 2018, s. 331-336. ISBN 978-1-5386-5710-2.
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2017

PODIVÍNSKÝ Jakub, ČEKAN Ondřej, LOJDA Jakub, ZACHARIÁŠOVÁ Marcela, KRČMA Martin a KOTÁSEK Zdeněk. Functional Verification Based Platform for Evaluating Fault Tolerance Properties. Microprocessors and Microsystems, roč. 52, č. 5, 2017, s. 145-159. ISSN 0141-9331.
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STRNADEL Josef. On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking. In: Proceedings of the 2017 20th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2017, s. 352-355. ISBN 978-1-5386-2146-2.
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PODIVÍNSKÝ Jakub, LOJDA Jakub, ČEKAN Ondřej, PÁNEK Richard a KOTÁSEK Zdeněk. Reliability Analysis and Improvement of FPGA-based Robot Controller. In: Proceedings of the 2017 20th Euromicro Conference on Digital System Design. Vídeň: IEEE Computer Society, 2017, s. 337-344. ISBN 978-1-5386-2145-5.
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ČEKAN Ondřej a KOTÁSEK Zdeněk. A Probabilistic Context-Free Grammar Based Random Test Program Generation. In: Proceedings of 20th Euromicro Conference on Digital System Design. Vídeň: Technische Universität Wien, 2017, s. 356-359. ISBN 978-1-5386-2145-5.
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KRČMA Martin, LOJDA Jakub a KOTÁSEK Zdeněk. Triple Modular Redundancy Used in Field Programmable Neural Networks. In: Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017, s. 1-6. ISBN 978-1-5386-3299-4.
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KRČMA Martin a KOTÁSEK Zdeněk. Approximation accuracy of different FPNN types. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Fakulta informačních technologií ČVUT, 2017, s. 81-82. ISBN 978-80-01-06178-7.
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LOJDA Jakub a KOTÁSEK Zdeněk. A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Fakulta informačních technologií ČVUT, 2017, s. 79-80. ISBN 978-80-01-06178-7.
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PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. The Use of Functional Verification for Monitoring Impact of Faults in SRAM-based FPGAs. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Fakulta informačních technologií ČVUT, 2017, s. 81-82. ISBN 978-80-01-06178-7.
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ČEKAN Ondřej a KOTÁSEK Zdeněk. Random Test Stimuli Generation Based on a Probabilistic Grammar. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Fakulta informačních technologií ČVUT, 2017, s. 43-44. ISBN 978-80-01-06178-7.
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LOJDA Jakub a KOTÁSEK Zdeněk. Automatizace návrhu systémů odolných proti poruchám pomocí vysokoúrovňové syntézy. In: Počítačové architektury & diagnostika 2017. Smolenice: Slovenská technická univerzita v Bratislavě, 2017, s. 59-62. ISBN 978-80-972784-0-3.
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PÁNEK Richard. Systémy odolné proti poruchám - metodika návrhu řadiče rekonfigurace. In: Počítačové architektury & diagnostika 2017. Smolenice: Slovenská technická univerzita v Bratislavě, 2017, s. 24-27. ISBN 978-80-972784-0-3.
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SZURMAN Karel a KOTÁSEK Zdeněk. State Synchronization of Faulty Soft Core Processors in Reconfigurable TMR Architecture. In: Počítačové architektúry & diagnostika 2017. Smolenice: Slovenská technická univerzita v Bratislavě, 2017, s. 51-54. ISBN 978-80-972784-0-3.
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LOJDA Jakub, PODIVÍNSKÝ Jakub, KOTÁSEK Zdeněk a KRČMA Martin. Data Types and Operations Modifications: a Practical Approach to Fault Tolerance in HLS. In: Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017, s. 273-278. ISBN 978-1-5386-3299-4.
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LOJDA Jakub, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Redundant Data Types and Operations in HLS and their Use for a Robot Controller Unit Fault Tolerance Evaluation. In: Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017, s. 359-364. ISBN 978-1-5386-3299-4.
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KRČMA Martin, KOTÁSEK Zdeněk a LOJDA Jakub. Comparison of FPNNs Models Approximation Capabilities and FPGA Resources Utilization. In: Proceedings of IEEE 13th International Conference on Intelligent Computer Communication and Processing. Cluj-Nappoca: IEEE Computer Society, 2017, s. 125-132. ISBN 978-1-5386-3368-7.
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2016

STRNADEL Josef. Modeling and Analysis of Fault-Tolerant Systems by Means of UPPAAL SMC: Method and Benefits. In: Informal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Bratislava: Slovenská technická univerzita v Bratislavě, 2016, s. 32-37. ISBN 978-80-8086-256-5.
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PODIVÍNSKÝ Jakub, ČEKAN Ondřej, LOJDA Jakub a KOTÁSEK Zdeněk. Verification of Robot Controller for Evaluating Impacts of Faults in Electro-mechanical Systems. In: Proceedings of the 19th Euromicro Conference on Digital Systems Design. Limassol: IEEE Computer Society, 2016, s. 487-494. ISBN 978-1-5090-2816-0.
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ZACHARIÁŠOVÁ Marcela, BELEŠOVÁ Michaela a KOTÁSEK Zdeněk. Regression Test Suites Optimization for Application-specific Instruction-set Processors and Their Use for Dependability Analysis. In: Proceedings of the 19th Euromicro Conference on Digital Systems Design. Limassol Cyprus: IEEE Computer Society, 2016, s. 380-387. ISBN 978-1-5090-2816-0.
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KRČMA Martin, KOTÁSEK Zdeněk, LOJDA Jakub a KAŠTIL Jan. Comparison of FPNNs Approximation Capabilities. In: Proceedings of the Work in progress Session held in connection with DSD 2016. Limassol: Johannes Kepler University Linz, 2016, s. 1-2. ISBN 978-3-902457-46-2.
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STRNADEL Josef. On Creation and Analysis of Reliability Models by Means of Stochastic Timed Automata and Statistical Model Checking: Principle. In: Leveraging Applications of Formal Methods, Verification and Validation: Foundational Techniques. Lecture Notes in Computer Science, Vol. 9952. Cham: Springer International Publishing, 2016, s. 166-181. ISBN 978-3-319-47166-2. ISSN 0302-9743.
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RIŠA Michal. Scheduling and Synchronization on Multicores. In: Sborník příspěvků Česko-slovenského semináře pro studenty doktorského studia Počítačové architektury & diagnostika. Brno: Fakulta informačních technologií VUT v Brně, 2016, s. 10-13. ISBN 978-80-214-5376-0.
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PODIVÍNSKÝ Jakub. Funkční verifikace jako nástroj pro sledování vlivu poruch na elektro-mechanický systém. In: Počítačové architektury a diagnostika PAD 2016. Bořetice - Kraví Hora: Fakulta informačních technologií VUT v Brně, 2016, s. 101-104. ISBN 978-80-214-5376-0.
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KOTÁSEK Zdeněk a PODIVÍNSKÝ Jakub. Verification of Robot Controller for Evaluating Impacts of Faults in Electro-mechanical Systems. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 2016.
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LOJDA Jakub a KOTÁSEK Zdeněk. A Systematic Approach to the Description of Fault-tolerant Systems. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 2016.
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ČEKAN Ondřej. Generování testovacích stimulů. In: Počítačové architektury a diagnostika PAD 2016. Bořetice - Kraví Hora: Fakulta informačních technologií VUT v Brně, 2016, s. 97-100. ISBN 978-80-214-5376-0.
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ČEKAN Ondřej a KOTÁSEK Zdeněk. Software-implemented Fault-Tolerant Program Generation. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 2016. ISBN 978-80-01-05984-5.
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STRNADEL Josef a RIŠA Michal. On Analysis of Software Interrupt Limiters for Embedded Systems by Means of UPPAAL SMC. In: Proceedings of the 24th Austrian Workshop on Microelectronics. Villach: IEEE Computer Society Press, 2016, s. 45-50. ISBN 978-1-5090-1040-0.
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PODIVÍNSKÝ Jakub, ČEKAN Ondřej, LOJDA Jakub a KOTÁSEK Zdeněk. Functional Verification as a Tool for Monitoring Impact of Faults in SRAM-based FPGAs. In: Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016, s. 293-294. ISBN 978-1-5090-5602-6.
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ČEKAN Ondřej, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Random Stimuli Generation Based on a Stochastic Context-Free Grammar. In: Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016, s. 295-296. ISBN 978-1-5090-5602-6.
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LOJDA Jakub, PODIVÍNSKÝ Jakub, KRČMA Martin a KOTÁSEK Zdeněk. HLS-based Fault Tolerance Approach for SRAM-based FPGAs. In: Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016, s. 301-302. ISBN 978-1-5090-5602-6.
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2015

STRNADEL Josef. Comparison of Generally Applicable Mechanisms for Preventing Embedded Event-Driven Real-Time Systems from Interrupt Overloads. In: Proceedings of the 2015 4th Eastern European Regional Conference on the Engineering of Computer Based Systems. Brno: Vysoké učení technické v Brně, 2015, s. 39-44. ISBN 978-1-4673-7967-0.
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PODIVÍNSKÝ Jakub, ZACHARIÁŠOVÁ Marcela, ČEKAN Ondřej a KOTÁSEK Zdeněk. FPGA Prototyping and Accelerated Verification of ASIPs. In: IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015, s. 145-148. ISBN 978-1-4799-6780-3.
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ČEKAN Ondřej, ZACHARIÁŠOVÁ Marcela a KOTÁSEK Zdeněk. Universal Pseudo-random Generation of Assembler Codes for Processors. In: Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015, s. 70-73.
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PODIVÍNSKÝ Jakub, ZACHARIÁŠOVÁ Marcela a KOTÁSEK Zdeněk. Radiation Impact on Mechanical Application Driven by FPGA-based Controller. In: Proceedings of The Fourth Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015, s. 13-16.
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KRČMA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. Mapping trained neural networks to FPNNs. In: IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015, s. 157-160. ISBN 978-1-4799-6779-7.
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ZACHARIÁŠOVÁ Marcela a KOTÁSEK Zdeněk. Automation and Optimization of Coverage-driven Verification. In: Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015, s. 87-94. ISBN 978-1-4673-8035-5.
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ČEKAN Ondřej, PODIVÍNSKÝ Jakub a KOTÁSEK Zdeněk. Software Fault Tolerance: the Evaluation by Functional Verification. In: Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015, s. 284-287. ISBN 978-1-4673-8035-5.
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ČEKAN Ondřej. Principy generování verifikačních stimulů. In: Počítačové architektury a diagnostika PAD 2015. Zlín: Fakulta aplikované informatiky, Univerzita Tomáše Bati ve Zlíně, 2015, s. 13-18. ISBN 978-80-7454-522-1.
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PODIVÍNSKÝ Jakub. Využití funkční verifikace pro ověřování metodik pro zajištění odolnosti proti poruchám. In: Počítačové architektury a diagnostika PAD 2015. Zlín: Univerzita Tomáše Bati ve Zlíně, 2015, s. 7-12. ISBN 978-80-7454-522-1.
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KRČMA Martin, KOTÁSEK Zdeněk a KAŠTIL Jan. Fault Tolerant Field Programmable Neural Networks. In: 1st IEEE Nordic Circuits and Systems (NORCAS) Conference. Oslo: IEEE Computer Society, 2015, s. 1-4. ISBN 978-1-4673-6575-8.
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KRČMA Martin. FPNN - neuronové sítě v FPGA. In: Počítačové architektury a diagnostika PAD 2015. Zlín: Univerzita Tomáše Bati ve Zlíně, 2015, s. 81-86. ISBN 978-80-7454-522-1.
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PODIVÍNSKÝ Jakub, ČEKAN Ondřej, ZACHARIÁŠOVÁ Marcela a KOTÁSEK Zdeněk. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. Microprocessors and Microsystems, roč. 39, č. 8, 2015, s. 1215-1230. ISSN 0141-9331.
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2014

STRNADEL Josef a SLIMAŘÍK František. Impact of Software Fault Tolerance to Fault Effects in OS-Driven RT Systems. Computing and Informatics, roč. 33, č. 4, 2014, s. 757-782. ISSN 1335-9150.
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KOTÁSEK Zdeněk a MIČULKA Lukáš. Generic Partial Dynamic Reconfiguration Controller for Transient and Permanent Fault Mitigation in Fault Tolerant Systems Implemented Into FPGA. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014, s. 171-174. ISBN 978-0-7695-5074-9.
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STRNADEL Josef a POKORNÝ Martin. Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework. In: Proceedings of the 2014 17th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2014, s. 333-340. ISBN 978-1-4799-5793-4.
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PODIVÍNSKÝ Jakub, ZACHARIÁŠOVÁ Marcela a KOTÁSEK Zdeněk. Complex Control System for Testing Fault-Tolerance Methodologies. In: Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Dresden: COST, European Cooperation in Science and Technology, 2014, s. 24-27. ISBN 978-2-11-129175-1.
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ČEKAN Ondřej, ZACHARIÁŠOVÁ Marcela a KOTÁSEK Zdeněk. Solving of Constraint Satisfaction Problem. In: Proceedings of the 20th Conference STUDENT EEICT 2014. Volume 3. Brno: Fakulta informačních technologií VUT v Brně, 2014, s. 291-295. ISBN 978-80-214-4924-4.
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SZURMAN Karel. Synchronization Methodology for Fault Tolerant System Recovery After Its Failure. In: Počítačové architektury & diagnostika 2014. Malá Skála: Technická univerzita v Liberci, 2014, s. 111-116. ISBN 978-80-7494-027-9.
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MATUŠOVÁ Lucie, KAŠTIL Jan a KOTÁSEK Zdeněk. Automatic Construction of On-line Checking Circuits Based on Finite Automata. In: 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014, s. 326-332. ISBN 978-0-7695-5074-9.
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ZACHARIÁŠOVÁ Marcela. Application of Evolutionary Computing for Optimization of Functional Verification. In: Počítačové architektury a diagnostika 2014. Liberec: Technická univerzita v Liberci, 2014, s. 135-140. ISBN 978-80-7494-027-9.
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PODIVÍNSKÝ Jakub. Testing Fault-Tolerance Properties in FPGA based Electro-mechanical Applications. In: Počítačové architektury a diagnostika 2014. Liberec: Technická univerzita v Liberci, 2014, s. 13-18. ISBN 978-80-7494-027-9.
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ČEKAN Ondřej. Universal Generation of Test Vectors for Functional Verification. In: Počítačové architektury a diagnostika 2014. Liberec: Technická univerzita v Liberci, 2014, s. 44-49. ISBN 978-80-7494-027-9.
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2013

STRAKA Martin, KAŠTIL Jan, KOTÁSEK Zdeněk a MIČULKA Lukáš. Fault Tolerant System Design and SEU Injection Based Testing. Microprocessors and Microsystems, roč. 2013, č. 37, s. 155-173. ISSN 0141-9331.
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STRNADEL Josef. Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates. In: Architecture of Computing Systems - ARCS 2013. Lecture Notes in Computer Science, ISSN 0302-9743, Vol. 7767, roč. 2013. Berlin: Springer Verlag, 2013, s. 98-109. ISBN 978-3-642-36423-5. ISSN 0302-9743.
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STRNADEL Josef. On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems. In: Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Brno: IEEE Computer Society, 2013, s. 24-29. ISBN 978-1-4673-6133-0.
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SZURMAN Karel, KAŠTIL Jan, STRAKA Martin a KOTÁSEK Zdeněk. Fault Tolerant CAN Bus Control System Implemented into FPGA. In: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013. Karlovy Vary: IEEE Computer Society, 2013, s. 289-292. ISBN 978-1-4673-6136-1.
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ZACHARIÁŠOVÁ Marcela, PŘIKRYL Zdeněk, HRUŠKA Tomáš a KOTÁSEK Zdeněk. Automated Functional Verification of Application Specific Instruction-set Processors. IFIP Advances in Information and Communication Technology, roč. 4, č. 403, 2013, s. 128-138. ISSN 1868-4238.
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ZACHARIÁŠOVÁ Marcela, BOLCHINI Cristiana a KOTÁSEK Zdeněk. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. In: IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Karlovy Vary: IEEE Computer Society, 2013, s. 275-278. ISBN 978-1-4673-6133-0.
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MIČULKA Lukáš, STRAKA Martin a KOTÁSEK Zdeněk. Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area. In: 16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Santander: IEEE Computer Society, 2013, s. 227-234. ISBN 978-0-7695-5074-9.
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ZACHARIÁŠOVÁ Marcela, BOLCHINI Cristiana a KOTÁSEK Zdeněk. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. In: Proceedings of The Second Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Avignon: COST, European Cooperation in Science and Technology, 2013, s. 35-38. ISBN 978-2-11-129175-1.
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MIČULKA Lukáš. Metoda návrh systémů odolných proti poruchám do omezeného implementačního prostoru na bázi FPGA. In: Počítačové architektury & diagnostika 2013. Plzeň: Západočeská univerzita v Plzni, 2013, s. 63-68. ISBN 978-80-261-0270-0.
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SZURMAN Karel. Fault Tolerant CAN Bus Control System Implemented into FPGA and its synchronization after failure and recovery. In: Počítačové architektury & diagnostika 2013. Plzeň: Západočeská univerzita v Plzni, 2013, s. 21-26. ISBN 978-1-4673-6136-1.
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ZACHARIÁŠOVÁ Marcela. New Methods for Increasing Efficiency and Speed of Functional Verification Processes. In: Počítačové architektury a diagnostika PAD 2013. Plzeň: Západočeská univerzita v Plzni, 2013, s. 111-116. ISBN 978-80-261-0270-0.
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2012

STRNADEL Josef. Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems. In: Proceedings of the 15th International IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Tallin: IEEE Computer Society, 2012, s. 121-126. ISBN 978-1-4673-1188-5.
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STRAKA Martin, MIČULKA Lukáš, KAŠTIL Jan a KOTÁSEK Zdeněk. Test Platform for Fault Tolerant Systems Design Qualities Verification. In: 15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Tallin: IEEE Computer Society, 2012, s. 336-341. ISBN 978-1-4673-1185-4.
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KAŠTIL Jan, STRAKA Martin a KOTÁSEK Zdeněk. Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration. In: The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12). Annecy: Politecnico di Milano, 2012, s. 1-4.
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STRNADEL Josef a SLIMAŘÍK František. On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels. In: Proceedings of the 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Pistacaway: IEEE Computer Society, 2012, s. 272-279. ISBN 978-0-7695-4798-5.
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KAŠTIL Jan, STRAKA Martin, MIČULKA Lukáš a KOTÁSEK Zdeněk. Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. In: 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012, s. 250-257. ISBN 978-0-7695-4798-5.
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STRAKA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. Methodology for Reliability Analysis of FPGA-based Fault Tolerant Systems. In: CSE'2012 International Scientific Conference on Computer Science and Engineering. Košice: Technická univerzita v Košiciach, 2012, s. 146-153. ISBN 978-80-8143-049-7.
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MIČULKA Lukáš a KOTÁSEK Zdeněk. Design Sychronization after Partial Dynamic Reconfiguration of Fault Tolerant System. In: 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012, s. 20-21. ISBN 978-3-902457-33-2.
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ZACHARIÁŠOVÁ Marcela. Acceleration of Functional Verification in the Development Cycle of Hardware Systems. In: Počítačové architektury a diagnostika. Praha: České vysoké učení technické, 2012, s. 73-78. ISBN 978-80-01-05106-1.
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ZACHARIÁŠOVÁ Marcela a LENGÁL Ondřej. Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures. FIT-TR-2012-03, Brno: Fakulta informačních technologií VUT v Brně, 2012.
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ZACHARIÁŠOVÁ Marcela a LENGÁL Ondřej. Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures. Lecture Notes in Computer Science, roč. 2013, č. 7857, 2012, s. 266-273. ISSN 0302-9743.
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MIČULKA Lukáš. Metoda návrh systémů odolných proti poruchám do omezeného implementačního prostoru na bázi FPGA. In: Počítačové architektury & diagnostika 2012. Praha: Fakulta informačních technologií ČVUT, 2012, s. 109-115. ISBN 978-80-01-05106-1.
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STRAKA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. FPGA-based Fault Tolerant Architectures and Their Dependability Analysis. In: MEMICS'12 -- 8th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Fakulta informatiky MU, 2012, s. 1-1.
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STRNADEL Josef a RAJNOHA Peter. Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study. Acta Electrotechnica et Informatica, roč. 12, č. 4, 2012, s. 17-29. ISSN 1335-8243.
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KOTÁSEK Zdeněk a ŠKARVADA Jaroslav. Low Power Testing. Design and Test Technology foír Dependable Systems-on-Chip. Hershey: IGI Global, 2012, s. 395-412. ISBN 978-1-60960-212-3.
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2011

STRAKA Martin, KAŠTIL Jan, NOVOTNÝ Jaroslav a KOTÁSEK Zdeněk. Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, s. 397-398. ISBN 978-1-4244-9753-9.
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STRNADEL Josef. Návrh časově kritických systémů III: priorita úloh. Automa, roč. 2011, č. 2, s. 50-52. ISSN 1210-9592.
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BARTOŠ Pavel, KOTÁSEK Zdeněk a DOHNAL Jan. Decreasing Test Time by Scan Chain Reorganization. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, s. 371-374. ISBN 978-1-4244-9753-9.
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STRNADEL Josef. Návrh časově kritických systémů IV: realizace prostředky RTOS. Automa, roč. 2011, č. 4, s. 58-60. ISSN 1210-9592.
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BARTOŠ Pavel. Test Time Reduction by Scan Chain Reordering. In: Proceedings of the 17th Conference STUDENT EEICT 2011. Volume 3. Brno: Fakulta elektrotechniky a komunikačních technologií VUT v Brně, 2011, s. 564-568. ISBN 978-80-214-4273-3.
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STRAKA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems. In: 14th EUROMICRO Conference on Digital System Design. Oulu: IEEE Computer Society, 2011, s. 223-230. ISBN 978-0-7695-4494-6.
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RUMPLÍK Michal a STRNADEL Josef. On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits. In: Proceedings of the 14th Euromicro Conference on Digital System Design - Architectures, Methods and Tools 2011. Oulu: IEEE Computer Society, 2011, s. 367-374. ISBN 978-0-7695-4494-6.
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STRNADEL Josef. Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads. In: Proceedings of the Work in Progress Session held in connection with SEAA 2011, the 37th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2011, the 14th EUROMICRO Conference on Digital System Design. Oulu: Johannes Kepler University Linz, 2011, s. 21-22. ISBN 978-3-902457-30-1.
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BARTOŠ Pavel. Metody reorganizace řetězce scan. In: Počítačové architektury a diagnostika 2011. Bratislava: Vydavateľstvo STU, 2011, s. 97-102. ISBN 978-80-227-3552-0.
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BARTOŠ Pavel, KOTÁSEK Zdeněk a DOHNAL Jan. Decreasing Test Time by Scan Chain Reorganization. 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Vysoké učení technické v Brně, 2011. ISBN 978-80-214-4305-1.
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STRNADEL Josef. Proposal of Flexible Monitoring-Driven HW/SW Interrupt Management for Embedded COTS-Based Event-Triggered Real-Time Systems. In: Proceedings of the Work-in-Progress Session of the 32nd IEEE Real-Time Systems Symposium. Vienna: Technische Universität Wien, 2011, s. 29-32.
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2010

STRAKA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs. In: Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Wien: IEEE Computer Society, 2010, s. 173-176. ISBN 978-1-4244-6610-8.
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KOTÁSEK Zdeněk, ŠKARVADA Jaroslav a STRNADEL Josef. Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences. In: Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010, s. 364-369. ISBN 978-1-4244-6610-8.
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STRAKA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration. In: 13th EUROMICRO Conference on Digital System Design, DSD'2010. Lille: IEEE Computer Society, 2010, s. 365-372. ISBN 978-0-7695-4171-6.
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STRNADEL Josef. Task-Level Modeling and Design of Components for Construction of Dependable Time-Critical Systems Implemented by Means of RT Kernel. In: Sborník přednášek z 33. mezinárodní konference TD 2010 - DIAGON 2010. Zlín: Univerzita Tomáše Bati ve Zlíně, 2010, s. 99-104. ISBN 978-80-7318-940-2.
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STRAKA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. Methodology for Design of Highly Dependable Systems in FPGA. In: International Scientific Conference on Computer Science and Engineering. Košice: Technická univerzita v Košiciach, 2010, s. 186-193. ISBN 978-80-8086-164-3.
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ŠKARVADA Jaroslav, KOTÁSEK Zdeněk a STRNADEL Josef. The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. In: Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science, ISSN 0302-9743, Vol. 6274, roč. 2010. Berlin: Springer Verlag, 2010, s. 181-192. ISBN 978-3-642-15322-8. ISSN 0302-9743.
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KOTÁSEK Zdeněk, ŠKARVADA Jaroslav a STRNADEL Josef. The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. In: Proceedings of 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2010, s. 644-651. ISBN 978-0-7695-4171-6.
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STRAKA Martin, KAŠTIL Jan a KOTÁSEK Zdeněk. Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA. In: NORCHIP 2010. Tampere: IEEE Computer Society, 2010, s. 1-4. ISBN 978-1-4244-8971-8.
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STRNADEL Josef. Návrh časově kritických systémů I: specifikace a verifikace. Automa, roč. 2010, č. 10, s. 42-44. ISSN 1210-9592.
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STRNADEL Josef. Návrh časově kritických systémů II: úlohy reálného času. Automa, roč. 2010, č. 12, s. 18-19. ISSN 1210-9592.
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ŠKARVADA Jaroslav, KOTÁSEK Zdeněk a STRNADEL Josef. Optimalizace aplikace testu číslicových systémů pro nízký příkon. Brno: Fakulta informačních technologií VUT v Brně, 2010. ISBN 978-80-214-4209-2.
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KOTÁSEK Zdeněk, BIDLO Michal a JAROŠ Jiří, ed. Počítačové architektury a diagnostika. Brno: Fakulta informačních technologií VUT v Brně, 2010. ISBN 978-80-214-4140-8.
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2009

STRAKA Martin a KOTÁSEK Zdeněk. High Availability Fault Tolerant Architectures Implemented into FPGAs. In: 12th EUROMICRO Conference on Digital System Design DSD 2009. Patras: IEEE Computer Society, 2009, s. 108-116. ISBN 978-0-7695-3782-5.
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STRNADEL Josef. Overview of Mechanisms for Improving Reliability of Embedded Real-Time Systems. In: Proceedings of 32th International Conference TD - DIAGON 2009. Zlín: Univerzita Tomáše Bati ve Zlíně, 2009, s. 19-24. ISBN 978-80-7318-840-5.
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KOTÁSEK Zdeněk a STRAKA Martin. The Design of On-line Checkers and Their Use in Verification and Testing. Acta Electrotechnica et Informatica, roč. 2009, č. 3, s. 8-15. ISSN 1335-8243.
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STRNADEL Josef a RŮŽIČKA Richard. Testability Analysis Driven Data Path Modification And Controller Synthesis. In: Proceedings of 16th Electronic Devices and Systems IMAPS CS International Conference. Brno: Vysoké učení technické v Brně, 2009, s. 363-368. ISBN 978-80-214-3933-7.
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STRAKA Martin a KOTÁSEK Zdeněk. Reliability Models for Fault Tolerant Architectures Based on FPGA. In: 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Fakulta informatiky MU, 2009, s. 239-239. ISBN 978-80-87342-04-6.
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2008

STRNADEL Josef, PEČENKA Tomáš a KOTÁSEK Zdeněk. Measuring Design for Testability Tool Effectiveness by Means of FITTest_BENCH06 Benchmark Circuits. Computing and Informatics, roč. 27, č. 6, 2008, s. 913-930. ISSN 1335-9150.
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STRNADEL Josef. Analýza a zlepšení testovatelnosti číslicových obvodů na úrovni meziregistrových přenosů. Brno: Fakulta informačních technologií VUT v Brně, 2008. ISBN 978-80-214-3599-5.
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SEKANINA Lukáš, STAREČEK Lukáš, KOTÁSEK Zdeněk a GAJDA Zbyšek. Polymorphic Gates in Design and Test of Digital Circuits. International Journal of Unconventional Computing, roč. 4, č. 2, 2008, s. 125-142. ISSN 1548-7199.
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STRAKA Martin. Checkers Design for Communication Protocols Based on FPGAs. In: Proceedings of the 14th Conference STUDENT EEICT 2008 Volume 4. Brno: Fakulta informačních technologií VUT v Brně, 2008, s. 467-473. ISBN 978-80-214-3617-6.
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STAREČEK Lukáš, SEKANINA Lukáš a KOTÁSEK Zdeněk. Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. In: Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008, s. 255-258. ISBN 978-1-4244-2276-0.
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STRAKA Martin, KOTÁSEK Zdeněk a WINTER Jan. Digital Systems Architectures Based on On-line Checkers. In: 11th EUROMICRO Conference on Digital System Design DSD 2008. Parma: IEEE Computer Society, 2008, s. 81-87. ISBN 978-0-7695-3277-6.
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PEČENKA Tomáš. Prostředky a metody pro automatické generování testovacích obvodů. Brno: Fakulta informačních technologií VUT v Brně, 2008. ISBN 978-80-214-3603-9.
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STRNADEL Josef. Testability Enhancement of Multilevel Designs Guided by Testability Analysis Method. In: Proceedings of Electronic Devices and Systems IMAPS CS International Conference. Brno: Vysoké učení technické v Brně, 2008, s. 367-372. ISBN 978-80-214-3717-3.
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STRNADEL Josef. TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path. In: Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2008, s. 865-872. ISBN 978-0-7695-3277-6.
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PEČENKA Tomáš, SEKANINA Lukáš a KOTÁSEK Zdeněk. Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability. ACM Transactions on Design Automation of Electronic Systems, roč. 13, č. 3, 2008, s. 1-21. ISSN 1084-4309.
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ŠKARVADA Jaroslav, KOTÁSEK Zdeněk a HERRMAN Tomáš. Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. Microprocessors and Microsystems, roč. 32, č. 5, 2008, s. 296-302. ISSN 0141-9331.
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ŠKARVADA Jaroslav, KOTÁSEK Zdeněk a HERRMAN Tomáš. Power Conscious RTL Test Scheduling. In: Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2008, s. 721-728. ISBN 978-0-7695-3277-6.
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ŠKARVADA Jaroslav. Optimalizace testu pro nízký příkon. In: Počítačové architektury a diagnostika 2008. Liberec: Technická univerzita v Liberci, 2008, s. 103-111. ISBN 978-80-7372-378-1.
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STRAKA Martin a KOTÁSEK Zdeněk. Design of FPGA-Based Dependable Systems. In: 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masarykova universita, 2008, s. 240-247. ISBN 978-80-7355-082-0.
Detail

ŠKARVADA Jaroslav, KOTÁSEK Zdeněk a HERRMAN Tomáš. Power Conscious RTL Test Scheduling. In: 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masarykova universita, 2008, s. 265-265. ISBN 978-80-7355-082-0.
Detail

HERRMAN Tomáš. Identifikace testovatelných bloků v obvodu na úrovni RT. In: Počítačové architektury a diagnostika 2008. Liberec: Technická univerzita v Liberci, 2008, s. 25-35. ISBN 978-80-7372-378-1.
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2007

STRAKA Martin. VHDL Design of Educational, Modern and Open-Architecture CPU. In: Proceedings of the 13th Conference STUDENT EEICT 2007 Volume 4. Brno: Vysoké učení technické v Brně, 2007, s. 457-461. ISBN 978-80-214-3410-3.
Detail

ŠKARVADA Jaroslav. RT Level Power Consumption Estimation Tool. In: Proceedings of the 13th Conference STUDENT EEICT 2007 Volume 4. Brno: Vysoké učení technické v Brně, 2007, s. 467-471. ISBN 80-214-3410-3.
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TOBOLA Jiří, KOTÁSEK Zdeněk, KOŘENEK Jan, MARTÍNEK Tomáš a STRAKA Martin. Online Protocol Testing for FPGA Based Fault Tolerant Systems. In: 10th EUROMICRO Conference on Digital System Design DSD 2007. Lubeck, Germany: IEEE Computer Society, 2007, s. 676-679. ISBN 0-7695-2978-X.
Detail

STRAKA Martin, TOBOLA Jiří a KOTÁSEK Zdeněk. Checker Design for On-line Testing of Xilinx FPGA Communication. In: The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Rome: IEEE Computer Society, 2007, s. 152-160. ISBN 0-7695-2885-6.
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STRNADEL Josef. Educational Toolset for Experimenting with Optimizations in the Area of Cost/Quality Trade-Offs Related to Digital Circuit Diagnosis. In: Proceedings of 14th Electronic Devices and Systems IMAPS CS International Conference. Brno: Vysoké učení technické v Brně, 2007, s. 333-338. ISBN 978-80-214-3470-7.
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STRNADEL Josef. On Encoding and Utilization of Diagnostic Information Extracted from Design-Data for Testability Analysis Purposes. In: Proceedings of the 6th Electronic Circuits and Systems Conference. Bratislava: Slovenská technická univerzita v Bratislavě, 2007, s. 171-176. ISBN 978-80-227-2697-9.
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ŠKARVADA Jaroslav, HERRMAN Tomáš a KOTÁSEK Zdeněk. Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. In: 10th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN Architectures, Methods and Tools (DSD 2007). Lübeck: IEEE Computer Society, 2007, s. 611-618. ISBN 0-7695-2978-X.
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RŮŽIČKA Richard a STRNADEL Josef. Test Controller Synthesis Constrained by Circuit Testability Analysis. In: Proceedings of 10th Euromicro Conference on Digital System Design, Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society Press, 2007, s. 626-633. ISBN 0-7695-2978-X.
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HERRMAN Tomáš. Metodika identifikace Testovatelných bloků v obvodu na úrovni RT. In: Počítačové architektury a diagnostika 2007. Plzeň: Západočeská univerzita v Plzni, 2007, s. 67-76. ISBN 978-80-7043-605-9.
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ŠKARVADA Jaroslav. Optimalizace plánování testu vzhledem k příkonu. In: Počítačové architektury a diagnostika 2007. Plzeň: Západočeská univerzita v Plzni, 2007, s. 85-92. ISBN 978-80-7043-605-9.
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KOTÁSEK Zdeněk a KUBEK Ján. Finite State Machine Localisation Based on IP Softcores Analysis. In: 6th Electronic Circuits and Systems Conference. Conference Proceedings. Bratislava: Slovenská technická univerzita v Bratislavě, 2007, s. 137-142. ISBN 978-80-227-2697-9.
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ŠKARVADA Jaroslav, HERRMAN Tomáš a KOTÁSEK Zdeněk. RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool. In: IEEE 8th Workshop on RTL and High Level Testing. Beijing: Institute of Computing Technology, Chinese Academy of Sciences, 2007, s. 175-181.
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HERRMAN Tomáš. Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. In: MEMICS proceedings 2007. Brno: Ing. Zdeněk Novotný, CSc., 2007, s. 269-269. ISBN 978-80-7355-077-6.
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ŠKARVADA Jaroslav. RT Level Test Optimization for Low Power Consumption. In: MEMICS proceedings 2007. Brno: Ing. Zdeněk Novotný, CSc., 2007, s. 185-192. ISBN 978-80-7355-077-6.
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RŮŽIČKA Richard. Podpora návrhu pro snadnou testovatelnost číslicových obvodů popsaných na úrovni meziregistrových přenosů. Brno: Fakulta informačních technologií VUT v Brně, 2007. ISBN 978-80-214-3551-3.
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2006

STRNADEL Josef a DHALI Arghya. Novel Optimizing Approach in the Area of STEP-Based Construction of Sessionless, Power-Constrainted, TAM and Time Optimal Test Schedules. In: Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS). Los Alamitos, CA: IEEE Computer Society, 2006, s. 360-367. ISBN 0-7695-2546-6.
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KOTÁSEK Zdeněk a STRNADEL Josef. SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. In: Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS). Los Alamitos, CA: IEEE Computer Society, 2006, s. 497-498. ISBN 0-7695-2546-6.
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STRNADEL Josef. Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space. In: Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Vydavatelství ČVUT, 2006, s. 161-162. ISBN 1-4244-0184-4.
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ŠKARVADA Jaroslav. Test Scheduling for SOC under Power Constraints. In: Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Vydavatelství ČVUT, 2006, s. 91-93. ISBN 1-4244-0184-4.
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ŠKARVADA Jaroslav a RŮŽIČKA Richard. Using Petri Nets for RT Level Digital Systems Test Scheduling. In: Proceedings of 1st International Workshop on Formal Models (WFM'06). Ostrava: MARQ, 2006, s. 79-86. ISBN 80-86840-20-4.
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HERRMAN Tomáš. Formal Model of Testable Block. In: Proceedings of 12th Conference Student EEICT 2006, Volume 4. Brno: Fakulta elektrotechniky a komunikačních technologií VUT v Brně, 2006, s. 451-455. ISBN 80-214-3163-6.
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ŠKARVADA Jaroslav. GA Based Test Scheduling Under Power Constraints. In: Proceedings of 12th Conference Student EEICT 2006, Volume 4. Brno: Fakulta elektrotechniky a komunikačních technologií VUT v Brně, 2006, s. 461-465. ISBN 80-214-3163-6.
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PEČENKA Tomáš, KOTÁSEK Zdeněk a SEKANINA Lukáš. FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties. In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006, s. 285-289. ISBN 1424401844.
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PEČENKA Tomáš, STRNADEL Josef, KOTÁSEK Zdeněk a SEKANINA Lukáš. Testability Estimation Based on Controllability and Observability Parameters. In: Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06). IEEE CS. Cavtat: IEEE Computer Society, 2006, s. 504-514. ISBN 0-7695-2609-8.
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HERRMAN Tomáš. Metodika aplikace testu obvodu založená na identifikaci Testovatelných bloků. In: Počítačové architektúry a diagnostika - zborník príspovkov. Bratislava: Ústav informatiky Slovenskej akadémie vied, 2006, s. 131-136. ISBN 80-969202-2-7.
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HERRMAN Tomáš. Testability Analysis Based on Formal Model. In: Proceedings of the Sevnth International Scientific Conference ECI 2006. Košice: Fakulta elektrotechniky a informatiky, Technická univerzita v Košiciach, 2006, s. 243-248. ISBN 80-8073-598-0.
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STRNADEL Josef. On Distribution of Testability Values in Scan-Layout State-Space. In: Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics. Košice: Technická univerzita v Košiciach, 2006, s. 308-313. ISBN 80-8073-598-0.
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PEČENKA Tomáš. Prostředky a metody pro automatické vytváření testovacích obvodů. In: Sborník příspěvků pracovního semináře Počítačové architektury & diagnostika pro studenty doktorského studia. Bratislava: Ústav informatiky Slovenskej akadémie vied, 2006, s. 13-18. ISBN 80-969202-2-7.
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ŠKARVADA Jaroslav. Optimalizace plánování testu číslicových systémů vzhledem k příkonu. In: Sborník příspěvků pracovního semináře Počítačové architektury & diagnostika pro studenty doktorského studia. Bratislava: Ústav informatiky Slovenskej akadémie vied, 2006, s. 143-148. ISBN 80-9692-0227.
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STRNADEL Josef. Testability Analysis and Improvements of Register-Transfer Level Digital Circuits. Computing and Informatics, roč. 25, č. 5, 2006, s. 441-464. ISSN 1335-9150.
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PEČENKA Tomáš a KOTÁSEK Zdeněk. I-path Scheduling Algorithm for RT Level Circuits. In: MEMICS 2006 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Mikulov, 2006, s. 174-181. ISBN 80-214-3287-X.
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2005

STRNADEL Josef. VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements. In: Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005, s. 190-193. ISBN 963-9364-48-7.
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PEČENKA Tomáš. At-speed Wiring Interconnects Testing on COMBO6 Card. In: Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005, s. 221-223. ISBN 963-9364-48-7.
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KOTÁSEK Zdeněk, STRNADEL Josef a PEČENKA Tomáš. Methodology of Selecting Scan-Based Testability Improving Technique. In: Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005, s. 186-189. ISBN 963-9364-48-7.
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RŮŽIČKA Richard. A Complex Approach to Digital RTL Circuit Testability - iFCoRT System. In: Informal Digest of Papers of the IEEE European Test Symposium 2005. Tallinn: Tallinna Tehnikaülikool, 2005, s. 156-157.
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KOTÁSEK Zdeněk a STRNADEL Josef a kol. Testing Tools for Training and Education. In: Proceedings of 12th International Conference on Mixed Design of Integrated Circuits and Systems. Krakow: Department of Microelectronics and Computer Science, Technical University of Lodz, 2005, s. 671-676. ISBN 83-919289-9-3.
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PEČENKA Tomáš, KOTÁSEK Zdeněk, SEKANINA Lukáš a STRNADEL Josef. Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. In: Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2005, s. 51-58. ISBN 0-7695-2399-4.
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PEČENKA Tomáš. Prostředky a metody pro automatické vytváření testovacích obvodů. In: Sborník příspěvků ze semináře Počítačové Architektury a Diagnostika. Praha: Fakulta elektrotechniky ČVUT, 2005, s. 135-140. ISBN 80-01-03298-1.
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RŮŽIČKA Richard. On the Petri Net Based Test Scheduling. In: Proceedings of the Work in Progress Session at Euromicro SEAA/DSD 2005. Linz: Johannes Kepler University Linz, 2005, s. 18-19. ISBN 3-902457-09-0.
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STRNADEL Josef, PEČENKA Tomáš a SEKANINA Lukáš. On Testability Analysis Driven Generation of Synthetic Register-Transfer Level Benchmark Circuits. In: Proceedings of 5th Electronic Circuits and Systems Conference. Bratislava: Slovenská technická univerzita v Bratislavě, 2005, s. 107-110.
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STRNADEL Josef a KOTÁSEK Zdeněk. Educational Tool for the Demonstration of Dft Principles Based on Scan Methodologies. In: Proceedings of 8th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2005, s. 420-427. ISBN 0-7695-2433-8.
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PEČENKA Tomáš. Generating Synthetic Benchmark Circuits with Predefined Testability Properties. In: Pre-Proc. 1st Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno, 2005, s. 200-209.
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